1/*
2 * BK Id: SCCS/s.cache.h 1.10 10/18/01 15:02:09 trini
3 */
4/*
5 * include/asm-ppc/cache.h
6 */
7#ifdef __KERNEL__
8#ifndef __ARCH_PPC_CACHE_H
9#define __ARCH_PPC_CACHE_H
10
11#include <linux/config.h>
12#include <asm/processor.h>
13
14/* bytes per L1 cache line */
15#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
16#define	L1_CACHE_LINE_SIZE	16
17#define LG_L1_CACHE_LINE_SIZE	4
18#define MAX_L1_COPY_PREFETCH	1
19#elif defined(CONFIG_PPC64BRIDGE)
20#define L1_CACHE_LINE_SIZE	128
21#define LG_L1_CACHE_LINE_SIZE	7
22#define MAX_L1_COPY_PREFETCH	1
23#else
24#define	L1_CACHE_LINE_SIZE  32
25#define LG_L1_CACHE_LINE_SIZE	5
26#define MAX_L1_COPY_PREFETCH	4
27#endif
28
29#define	L1_CACHE_BYTES L1_CACHE_LINE_SIZE
30#define	SMP_CACHE_BYTES L1_CACHE_BYTES
31
32#define	L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
33#define	L1_CACHE_PAGES		8
34
35#ifdef MODULE
36#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
37#else
38#define __cacheline_aligned					\
39  __attribute__((__aligned__(L1_CACHE_BYTES),			\
40		 __section__(".data.cacheline_aligned")))
41#endif
42
43#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
44extern void flush_dcache_range(unsigned long start, unsigned long stop);
45
46#endif /* __ASSEMBLY__ */
47
48/* prep registers for L2 */
49#define CACHECRBA       0x80000823      /* Cache configuration register address */
50#define L2CACHE_MASK	0x03	/* Mask for 2 L2 Cache bits */
51#define L2CACHE_512KB	0x00	/* 512KB */
52#define L2CACHE_256KB	0x01	/* 256KB */
53#define L2CACHE_1MB	0x02	/* 1MB */
54#define L2CACHE_NONE	0x03	/* NONE */
55#define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
56
57#ifdef CONFIG_8xx
58/* Cache control on the MPC8xx is provided through some additional
59 * special purpose registers.
60 */
61#define IC_CST		560	/* Instruction cache control/status */
62#define IC_ADR		561	/* Address needed for some commands */
63#define IC_DAT		562	/* Read-only data register */
64#define DC_CST		568	/* Data cache control/status */
65#define DC_ADR		569	/* Address needed for some commands */
66#define DC_DAT		570	/* Read-only data register */
67
68/* Commands.  Only the first few are available to the instruction cache.
69*/
70#define	IDC_ENABLE	0x02000000	/* Cache enable */
71#define IDC_DISABLE	0x04000000	/* Cache disable */
72#define IDC_LDLCK	0x06000000	/* Load and lock */
73#define IDC_UNLINE	0x08000000	/* Unlock line */
74#define IDC_UNALL	0x0a000000	/* Unlock all */
75#define IDC_INVALL	0x0c000000	/* Invalidate all */
76
77#define DC_FLINE	0x0e000000	/* Flush data cache line */
78#define DC_SFWT		0x01000000	/* Set forced writethrough mode */
79#define DC_CFWT		0x03000000	/* Clear forced writethrough mode */
80#define DC_SLES		0x05000000	/* Set little endian swap mode */
81#define DC_CLES		0x07000000	/* Clear little endian swap mode */
82
83/* Status.
84*/
85#define IDC_ENABLED	0x80000000	/* Cache is enabled */
86#define IDC_CERR1	0x00200000	/* Cache error 1 */
87#define IDC_CERR2	0x00100000	/* Cache error 2 */
88#define IDC_CERR3	0x00080000	/* Cache error 3 */
89
90#define DC_DFWT		0x40000000	/* Data cache is forced write through */
91#define DC_LES		0x20000000	/* Caches are little endian mode */
92#endif /* CONFIG_8xx */
93
94#endif
95#endif /* __KERNEL__ */
96