Searched refs:FPGA_PIN (Results 1 - 5 of 5) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/vr41xx/nec-eagle/
H A Dirq.c170 vr41xx_set_irq_trigger(FPGA_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH);
171 vr41xx_set_irq_level(FPGA_PIN, LEVEL_HIGH);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/vr41xx/
H A Deagle.h73 #define FPGA_PIN 5 macro
81 #define FPGA_CASCADE_IRQ GIU_IRQ(FPGA_PIN)
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/vr41xx/
H A Deagle.h73 #define FPGA_PIN 5 macro
81 #define FPGA_CASCADE_IRQ GIU_IRQ(FPGA_PIN)
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/vr41xx/
H A Deagle.h73 #define FPGA_PIN 5 macro
81 #define FPGA_CASCADE_IRQ GIU_IRQ(FPGA_PIN)
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/vr41xx/
H A Deagle.h73 #define FPGA_PIN 5 macro
81 #define FPGA_CASCADE_IRQ GIU_IRQ(FPGA_PIN)

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