1/* 2 * FILE NAME 3 * include/asm-mips/vr41xx/eagle.h 4 * 5 * BRIEF MODULE DESCRIPTION 6 * Include file for NEC Eagle board. 7 * 8 * Author: MontaVista Software, Inc. 9 * yyuasa@mvista.com or source@mvista.com 10 * 11 * Copyright 2001,2002 MontaVista Software Inc. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 24 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 26 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 27 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * You should have received a copy of the GNU General Public License along 30 * with this program; if not, write to the Free Software Foundation, Inc., 31 * 675 Mass Ave, Cambridge, MA 02139, USA. 32 */ 33#ifndef __NEC_EAGLE_H 34#define __NEC_EAGLE_H 35 36#include <asm/addrspace.h> 37#include <asm/vr41xx/vr41xx.h> 38 39/* 40 * Board specific address mapping 41 */ 42#define VR41XX_PCI_MEM1_BASE 0x10000000 43#define VR41XX_PCI_MEM1_SIZE 0x04000000 44#define VR41XX_PCI_MEM1_MASK 0x7c000000 45 46#define VR41XX_PCI_MEM2_BASE 0x14000000 47#define VR41XX_PCI_MEM2_SIZE 0x02000000 48#define VR41XX_PCI_MEM2_MASK 0x7e000000 49 50#define VR41XX_PCI_IO_BASE 0x16000000 51#define VR41XX_PCI_IO_SIZE 0x02000000 52#define VR41XX_PCI_IO_MASK 0x7e000000 53 54#define VR41XX_PCI_IO_START 0x01000000 55#define VR41XX_PCI_IO_END 0x01ffffff 56 57#define VR41XX_PCI_MEM_START 0x12000000 58#define VR41XX_PCI_MEM_END 0x15ffffff 59 60#define IO_PORT_BASE KSEG1ADDR(VR41XX_PCI_IO_BASE) 61#define IO_PORT_RESOURCE_START 0 62#define IO_PORT_RESOURCE_END VR41XX_PCI_IO_SIZE 63#define IO_MEM1_RESOURCE_START VR41XX_PCI_MEM1_BASE 64#define IO_MEM1_RESOURCE_END (VR41XX_PCI_MEM1_BASE + VR41XX_PCI_MEM1_SIZE) 65#define IO_MEM2_RESOURCE_START VR41XX_PCI_MEM2_BASE 66#define IO_MEM2_RESOURCE_END (VR41XX_PCI_MEM2_BASE + VR41XX_PCI_MEM2_SIZE) 67 68/* 69 * General-Purpose I/O Pin Number 70 */ 71#define VRC4173_PIN 1 72#define PCISLOT_PIN 4 73#define FPGA_PIN 5 74#define DCD_PIN 15 75 76/* 77 * Interrupt Number 78 */ 79#define VRC4173_CASCADE_IRQ GIU_IRQ(VRC4173_PIN) 80#define PCISLOT_IRQ GIU_IRQ(PCISLOT_PIN) 81#define FPGA_CASCADE_IRQ GIU_IRQ(FPGA_PIN) 82#define DCD_IRQ GIU_IRQ(DCD_PIN) 83 84#define SDBINT_IRQ_BASE 88 85#define DEG_IRQ (SDBINT_IRQ_BASE + 1) 86#define ENUM_IRQ (SDBINT_IRQ_BASE + 2) 87#define SIO1INT_IRQ (SDBINT_IRQ_BASE + 3) 88#define SIO2INT_IRQ (SDBINT_IRQ_BASE + 4) 89#define PARINT_IRQ (SDBINT_IRQ_BASE + 5) 90#define SDBINT_IRQ_LAST PARINT_IRQ 91 92#define PCIINT_IRQ_BASE 96 93#define CP_INTA_IRQ (PCIINT_IRQ_BASE + 0) 94#define CP_INTB_IRQ (PCIINT_IRQ_BASE + 1) 95#define CP_INTC_IRQ (PCIINT_IRQ_BASE + 2) 96#define CP_INTD_IRQ (PCIINT_IRQ_BASE + 3) 97#define LANINTA_IRQ (PCIINT_IRQ_BASE + 4) 98#define PCIINT_IRQ_LAST LANINTA_IRQ 99 100/* 101 * On board Devices I/O Mapping 102 */ 103#define NEC_EAGLE_SIO1RB KSEG1ADDR(0x0DFFFEC0) 104#define NEC_EAGLE_SIO1TH KSEG1ADDR(0x0DFFFEC0) 105#define NEC_EAGLE_SIO1IE KSEG1ADDR(0x0DFFFEC2) 106#define NEC_EAGLE_SIO1IID KSEG1ADDR(0x0DFFFEC4) 107#define NEC_EAGLE_SIO1FC KSEG1ADDR(0x0DFFFEC4) 108#define NEC_EAGLE_SIO1LC KSEG1ADDR(0x0DFFFEC6) 109#define NEC_EAGLE_SIO1MC KSEG1ADDR(0x0DFFFEC8) 110#define NEC_EAGLE_SIO1LS KSEG1ADDR(0x0DFFFECA) 111#define NEC_EAGLE_SIO1MS KSEG1ADDR(0x0DFFFECC) 112#define NEC_EAGLE_SIO1SC KSEG1ADDR(0x0DFFFECE) 113 114#define NEC_EAGLE_SIO2TH KSEG1ADDR(0x0DFFFED0) 115#define NEC_EAGLE_SIO2IE KSEG1ADDR(0x0DFFFED2) 116#define NEC_EAGLE_SIO2IID KSEG1ADDR(0x0DFFFED4) 117#define NEC_EAGLE_SIO2FC KSEG1ADDR(0x0DFFFED4) 118#define NEC_EAGLE_SIO2LC KSEG1ADDR(0x0DFFFED6) 119#define NEC_EAGLE_SIO2MC KSEG1ADDR(0x0DFFFED8) 120#define NEC_EAGLE_SIO2LS KSEG1ADDR(0x0DFFFEDA) 121#define NEC_EAGLE_SIO2MS KSEG1ADDR(0x0DFFFEDC) 122#define NEC_EAGLE_SIO2SC KSEG1ADDR(0x0DFFFEDE) 123 124#define NEC_EAGLE_PIOPP_DATA KSEG1ADDR(0x0DFFFEE0) 125#define NEC_EAGLE_PIOPP_STATUS KSEG1ADDR(0x0DFFFEE2) 126#define NEC_EAGLE_PIOPP_CNT KSEG1ADDR(0x0DFFFEE4) 127#define NEC_EAGLE_PIOPP_EPPADDR KSEG1ADDR(0x0DFFFEE6) 128#define NEC_EAGLE_PIOPP_EPPDATA0 KSEG1ADDR(0x0DFFFEE8) 129#define NEC_EAGLE_PIOPP_EPPDATA1 KSEG1ADDR(0x0DFFFEEA) 130#define NEC_EAGLE_PIOPP_EPPDATA2 KSEG1ADDR(0x0DFFFEEC) 131 132#define NEC_EAGLE_PIOECP_DATA KSEG1ADDR(0x0DFFFEF0) 133#define NEC_EAGLE_PIOECP_CONFIG KSEG1ADDR(0x0DFFFEF2) 134#define NEC_EAGLE_PIOECP_EXTCNT KSEG1ADDR(0x0DFFFEF4) 135 136/* 137 * FLSHCNT Register 138 */ 139#define NEC_EAGLE_FLSHCNT KSEG1ADDR(0x0DFFFFA0) 140#define NEC_EAGLE_FLSHCNT_FRDY 0x80 141#define NEC_EAGLE_FLSHCNT_VPPE 0x40 142#define NEC_EAGLE_FLSHCNT_WP2 0x01 143 144/* 145 * FLSHBANK Register 146 */ 147#define NEC_EAGLE_FLSHBANK KSEG1ADDR(0x0DFFFFA4) 148#define NEC_EAGLE_FLSHBANK_S_BANK2 0x40 149#define NEC_EAGLE_FLSHBANK_S_BANK1 0x20 150#define NEC_EAGLE_FLSHBANK_BNKQ4 0x10 151#define NEC_EAGLE_FLSHBANK_BNKQ3 0x08 152#define NEC_EAGLE_FLSHBANK_BNKQ2 0x04 153#define NEC_EAGLE_FLSHBANK_BNKQ1 0x02 154#define NEC_EAGLE_FLSHBANK_BNKQ0 0x01 155 156/* 157 * SWITCH Setting Register 158 */ 159#define NEC_EAGLE_SWTCHSET KSEG1ADDR(0x0DFFFFA8) 160#define NEC_EAGLE_SWTCHSET_DP2SW4 0x80 161#define NEC_EAGLE_SWTCHSET_DP2SW3 0x40 162#define NEC_EAGLE_SWTCHSET_DP2SW2 0x20 163#define NEC_EAGLE_SWTCHSET_DP2SW1 0x10 164#define NEC_EAGLE_SWTCHSET_DP1SW4 0x08 165#define NEC_EAGLE_SWTCHSET_DP1SW3 0x04 166#define NEC_EAGLE_SWTCHSET_DP1SW2 0x02 167#define NEC_EAGLE_SWTCHSET_DP1SW1 0x01 168 169/* 170 * PPT Parallel Port Device Controller 171 */ 172#define NEC_EAGLE_PPT_WRITE_DATA KSEG1ADDR(0x0DFFFFB0) 173#define NEC_EAGLE_PPT_READ_DATA KSEG1ADDR(0x0DFFFFB2) 174#define NEC_EAGLE_PPT_CNT KSEG1ADDR(0x0DFFFFB4) 175#define NEC_EAGLE_PPT_CNT2 KSEG1ADDR(0x0DFFFFB4) 176 177/* Control Register */ 178#define NEC_EAGLE_PPT_INTMSK 0x20 179#define NEC_EAGLE_PPT_PARIINT 0x10 180#define NEC_EAGLE_PPT_SELECTIN 0x08 181#define NEC_EAGLE_PPT_INIT 0x04 182#define NEC_EAGLE_PPT_AUTOFD 0x02 183#define NEC_EAGLE_PPT_STROBE 0x01 184 185/* Control Rgister 2 */ 186#define NEC_EAGLE_PPT_PAREN 0x80 187#define NEC_EAGLE_PPT_AUTOEN 0x20 188#define NEC_EAGLE_PPT_BUSY 0x10 189#define NEC_EAGLE_PPT_ACK 0x08 190#define NEC_EAGLE_PPT_PE 0x04 191#define NEC_EAGLE_PPT_SELECT 0x02 192#define NEC_EAGLE_PPT_FAULT 0x01 193 194/* 195 * LEDWR Register 196 */ 197#define NEC_EAGLE_LEDWR1 KSEG1ADDR(0x0DFFFFC0) 198#define NEC_EAGLE_LEDWR2 KSEG1ADDR(0x0DFFFFC4) 199 200/* 201 * SDBINT Register 202 */ 203#define NEC_EAGLE_SDBINT KSEG1ADDR(0x0DFFFFD0) 204#define NEC_EAGLE_SDBINT_PARINT 0x20 205#define NEC_EAGLE_SDBINT_SIO2INT 0x10 206#define NEC_EAGLE_SDBINT_SIO1INT 0x08 207#define NEC_EAGLE_SDBINT_ENUM 0x04 208#define NEC_EAGLE_SDBINT_DEG 0x02 209 210/* 211 * SDB INTMSK Register 212 */ 213#define NEC_EAGLE_SDBINTMSK KSEG1ADDR(0x0DFFFFD4) 214#define NEC_EAGLE_SDBINTMSK_MSKPAR 0x20 215#define NEC_EAGLE_SDBINTMSK_MSKSIO2 0x10 216#define NEC_EAGLE_SDBINTMSK_MSKSIO1 0x08 217#define NEC_EAGLE_SDBINTMSK_MSKENUM 0x04 218#define NEC_EAGLE_SDBINTMSK_MSKDEG 0x02 219 220/* 221 * RSTREG Register 222 */ 223#define NEC_EAGLE_RSTREG KSEG1ADDR(0x0DFFFFD8) 224#define NEC_EAGLE_RST_RSTSW 0x02 225#define NEC_EAGLE_RST_LEDOFF 0x01 226 227/* 228 * PCI INT Rgister 229 */ 230#define NEC_EAGLE_PCIINTREG KSEG1ADDR(0x0DFFFFDC) 231#define NEC_EAGLE_PCIINT_LANINT 0x10 232#define NEC_EAGLE_PCIINT_CP_INTD 0x08 233#define NEC_EAGLE_PCIINT_CP_INTC 0x04 234#define NEC_EAGLE_PCIINT_CP_INTB 0x02 235#define NEC_EAGLE_PCIINT_CP_INTA 0x01 236 237/* 238 * PCI INT Mask Register 239 */ 240#define NEC_EAGLE_PCIINTMSKREG KSEG1ADDR(0x0DFFFFE0) 241#define NEC_EAGLE_PCIINTMSK_MSKLANINT 0x10 242#define NEC_EAGLE_PCIINTMSK_MSKCP_INTD 0x08 243#define NEC_EAGLE_PCIINTMSK_MSKCP_INTC 0x04 244#define NEC_EAGLE_PCIINTMSK_MSKCP_INTB 0x02 245#define NEC_EAGLE_PCIINTMSK_MSKCP_INTA 0x01 246 247/* 248 * CLK Division Register 249 */ 250#define NEC_EAGLE_CLKDIV KSEG1ADDR(0x0DFFFFE4) 251#define NEC_EAGLE_CLKDIV_PCIDIV1 0x10 252#define NEC_EAGLE_CLKDIV_PCIDIV0 0x08 253#define NEC_EAGLE_CLKDIV_VTDIV2 0x04 254#define NEC_EAGLE_CLKDIV_VTDIV1 0x02 255#define NEC_EAGLE_CLKDIV_VTDIV0 0x01 256 257/* 258 * Source Revision Register 259 */ 260#define NEC_EAGLE_REVISION KSEG1ADDR(0x0DFFFFE8) 261 262#endif /* __NEC_EAGLE_H */ 263