Searched refs:BIT4 (Results 1 - 18 of 18) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-arm/arch-integrator/
H A Dbits.h30 #define BIT4 0x00000010 macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-arm/arch-integrator/
H A Dbits.h30 #define BIT4 0x00000010 macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/scsi/
H A Dtmscsim.h284 #define BIT4 0x00000010 macro
307 #define SRB_MSGIN_MULTI BIT4
324 #define PARITY_ERROR BIT4
339 #define ENABLE_TIMER BIT4
386 #define EN_TAG_QUEUEING BIT4
492 #define TAG_QUEUEING_ BIT4
499 #define NO_SEEK BIT4
547 #define COUNT_2_ZERO BIT4
556 #define SERVICE_REQUEST BIT4
579 #define PARITY_ERR_REPO BIT4
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/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/galileo-boards/evb64120A/
H A Ddma.h21 #define DECREMENT_DEST_ADDRESS BIT4
H A Dcore.h21 #define BIT4 0x00000010 macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/galileo-boards/evb64120A/
H A Ddma.h21 #define DECREMENT_DEST_ADDRESS BIT4
H A Dcore.h21 #define BIT4 0x00000010 macro
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/galileo-boards/evb64120A/
H A Ddma.h21 #define DECREMENT_DEST_ADDRESS BIT4
H A Dcore.h21 #define BIT4 0x00000010 macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/galileo-boards/evb64120A/
H A Ddma.h21 #define DECREMENT_DEST_ADDRESS BIT4
H A Dcore.h21 #define BIT4 0x00000010 macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/galileo-boards/ev64120/
H A Di2o.c467 return (regData & BIT4); /* if set return '1' (true), else '0' (false) */
479 GT_REG_WRITE(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, BIT4);
497 regData | BIT4);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/linux/
H A Dsynclink.h24 #define BIT4 0x0010 macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/linux/
H A Dsynclink.h24 #define BIT4 0x0010 macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/char/
H A Dsynclinkmp.c447 #define SYNCD BIT4
448 #define FLGD BIT4
463 #define FRME BIT4
464 #define RBIT BIT4
2297 * BIT4 = COF (counter overflow)
2349 * BIT4 = COF (counter overflow)
2551 if (timerstatus0 & (BIT5 | BIT4))
2555 if (timerstatus1 & (BIT5 | BIT4))
4409 case 7: RegValue |= BIT4 + BIT2; break;
4411 case 5: RegValue |= BIT5 + BIT4
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H A Dsynclink.c524 #define RECEIVE_DATA BIT4
541 #define RXSTATUS_RXBOUND BIT4
580 #define TXSTATUS_EOF_SENT BIT4
581 #define TXSTATUS_EOM_SENT BIT4
601 #define MISCSTATUS_CTS BIT4
626 #define SICR_CTS_INACTIVE BIT4
627 #define SICR_CTS (BIT5+BIT4)
661 #define TXSTATUS_EOF BIT4
5050 RegValue |= BIT4;
5310 RegValue |= BIT4; /* enabl
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/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/char/pcmcia/
H A Dsynclink_cs.c882 #define CMD_START_TIMER BIT4
3492 val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
3579 val |= BIT4;
3582 val |= BIT4 + BIT2;
3585 val |= BIT4 + BIT3;
3621 val |= BIT4;
3988 val |= BIT4;
4146 if (!(status & BIT7) || (status & BIT4))
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/acpi/include/
H A Dacmacros.h55 #define BIT4(x) ((((x) & 0x10) > 0) ? 1 : 0) macro

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