/linux-master/drivers/net/wireless/ath/ath9k/ |
H A D | htc_drv_init.c | 234 static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset) argument 239 __be32 val, reg = cpu_to_be32(reg_offset); 248 reg_offset, r); 302 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset) argument 308 cpu_to_be32(reg_offset), 319 reg_offset, r); 323 static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset) argument 333 cpu_to_be32(reg_offset); 346 static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset) argument 353 ath9k_regwrite_buffer(hw_priv, val, reg_offset); 383 ath9k_reg_rmw_buffer(void *hw_priv, u32 reg_offset, u32 set, u32 clr) argument 466 ath9k_reg_rmw_single(void *hw_priv, u32 reg_offset, u32 set, u32 clr) argument 489 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) argument [all...] |
/linux-master/drivers/mfd/ |
H A D | wm5102-tables.c | 124 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, 125 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, 126 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, 127 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, 130 .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1 133 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 136 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1 140 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 143 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 146 .reg_offset [all...] |
H A D | da9055-core.c | 223 .reg_offset = 0, 227 .reg_offset = 0, 231 .reg_offset = 0, 235 .reg_offset = 0, 239 .reg_offset = 1,
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/linux-master/drivers/net/ipa/ |
H A D | ipa_main.c | 215 iowrite32(val, ipa->reg_virt + reg_offset(reg)); 230 offset = reg_offset(reg); 262 iowrite32(val, ipa->reg_virt + reg_offset(reg)); 277 offset = reg_offset(reg); 318 iowrite32(val, ipa->reg_virt + reg_offset(reg)); 334 iowrite32(val, ipa->reg_virt + reg_offset(reg)); 376 iowrite32(0, ipa->reg_virt + reg_offset(reg)); 388 iowrite32(val, ipa->reg_virt + reg_offset(reg)); 401 iowrite32(val, ipa->reg_virt + reg_offset(reg)); 405 offset = reg_offset(re [all...] |
H A D | ipa_interrupt.c | 80 offset = reg_offset(reg); 129 offset = reg_offset(reg); 147 iowrite32(pending, ipa->reg_virt + reg_offset(reg)); 160 iowrite32(ipa->interrupt->enabled, ipa->reg_virt + reg_offset(reg)); 251 iowrite32(0, ipa->reg_virt + reg_offset(reg));
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H A D | gsi.c | 202 iowrite32(val, gsi->virt + reg_offset(reg)); 230 iowrite32(~0, gsi->virt + reg_offset(reg)); 233 iowrite32(val, gsi->virt + reg_offset(reg)); 245 iowrite32(0, gsi->virt + reg_offset(reg)); 263 iowrite32(~0, gsi->virt + reg_offset(reg)); 266 iowrite32(val, gsi->virt + reg_offset(reg)); 279 iowrite32(0, gsi->virt + reg_offset(reg)); 292 iowrite32(val, gsi->virt + reg_offset(reg)); 312 iowrite32(val, gsi->virt + reg_offset(reg)); 330 iowrite32(ERROR_INT, gsi->virt + reg_offset(re [all...] |
/linux-master/drivers/clk/qcom/ |
H A D | clk-regmap-mux-div.c | 33 ret = regmap_update_bits(md->clkr.regmap, CFG_RCGR + md->reg_offset, 38 ret = regmap_update_bits(md->clkr.regmap, CMD_RCGR + md->reg_offset, 45 ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, 65 regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val); 72 regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val);
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/linux-master/drivers/media/platform/nxp/imx-jpeg/ |
H A D | mxc-jpeg-hw.c | 12 #define print_wrapper_reg(dev, base_address, reg_offset)\ 13 internal_print_wrapper_reg(dev, (base_address), #reg_offset,\ 14 (reg_offset)) 15 #define internal_print_wrapper_reg(dev, base_address, reg_name, reg_offset) {\ 17 val = readl((base_address) + (reg_offset));\
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/linux-master/drivers/mmc/host/ |
H A D | dw_mmc-pltfm.c | 74 u32 clk_phase[2] = {0}, reg_offset, reg_shift; local 87 of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); 94 regmap_write(sys_mgr_base_addr, reg_offset, hs_timing);
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/linux-master/drivers/gpio/ |
H A D | gpio-bcm-kona.c | 131 u32 val, reg_offset; local 142 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); 144 val = readl(reg_base + reg_offset); 146 writel(val, reg_base + reg_offset); 158 u32 val, reg_offset; local 166 reg_offset = GPIO_IN_STATUS(bank_id); 168 reg_offset = GPIO_OUT_STATUS(bank_id); 171 val = readl(reg_base + reg_offset); 222 u32 val, reg_offset; local 233 reg_offset [all...] |
/linux-master/arch/loongarch/kernel/ |
H A D | kgdb.c | 109 int reg_offset, reg_size; local 114 reg_offset = dbg_reg_def[regno].offset; 117 if (reg_offset == -1) 122 memcpy(mem, (void *)regs + reg_offset, reg_size); local 137 memcpy(mem, (void *)¤t->thread.fpu.fcc + reg_offset, reg_size); 140 memcpy(mem, (void *)¤t->thread.fpu.fpr[reg_offset], reg_size); 152 int reg_offset, reg_size; local 157 reg_offset = dbg_reg_def[regno].offset; 160 if (reg_offset == -1) 165 memcpy((void *)regs + reg_offset, me [all...] |
/linux-master/drivers/gpu/drm/msm/disp/mdp5/ |
H A D | mdp5_pipe.c | 156 uint32_t reg_offset, uint32_t caps) 166 hwpipe->reg_offset = reg_offset; 154 mdp5_pipe_init(struct drm_device *dev, enum mdp5_pipe pipe, uint32_t reg_offset, uint32_t caps) argument
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/linux-master/drivers/irqchip/ |
H A D | irq-owl-sirq.c | 46 u16 reg_offset[NUM_SIRQ]; member in struct:owl_sirq_params 59 .reg_offset = { 0, 0, 0 }, 65 .reg_offset = { INTC_EXTCTL0, INTC_EXTCTL1, INTC_EXTCTL2 }, 98 val = readl_relaxed(data->base + data->params->reg_offset[index]); 111 val = readl_relaxed(data->base + data->params->reg_offset[index]); 116 writel_relaxed(extctl, data->base + data->params->reg_offset[index]);
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/linux-master/drivers/clk/microchip/ |
H A D | clk-mpfs-ccc.c | 47 u32 reg_offset; member in struct:mpfs_ccc_pll_hw_clock 76 void __iomem *mult_addr = ccc_hw->base + ccc_hw->reg_offset; 105 .reg_offset = _offset, \ 121 u32 reg_offset; member in struct:mpfs_ccc_out_hw_clock 128 .reg_offset = _offset, \ 174 out_hw->reg_offset;
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | jpeg_v4_0_3.c | 505 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); local 517 reg_offset, 0); 520 reg_offset, 525 reg_offset, lower_32_bits(ring->gpu_addr)); 529 reg_offset, upper_32_bits(ring->gpu_addr)); 532 reg_offset, 0); 535 reg_offset, 0); 538 reg_offset, 0x00000002L); 541 reg_offset, ring->ring_size / 4); 544 reg_offset); 821 uint32_t reg_offset = (reg << 2); local 862 uint32_t reg_offset = (reg << 2); local 898 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); local 920 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); local [all...] |
H A D | amdgpu_amdkfd_gfx_v10.h | 57 uint32_t *reg_offset,
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H A D | hdp_v6_0.c | 38 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 40 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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H A D | hdp_v7_0.c | 35 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 37 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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/linux-master/drivers/fpga/ |
H A D | socfpga.c | 134 static u32 socfpga_fpga_readl(struct socfpga_fpga_priv *priv, u32 reg_offset) argument 136 return readl(priv->fpga_base_addr + reg_offset); 139 static void socfpga_fpga_writel(struct socfpga_fpga_priv *priv, u32 reg_offset, argument 142 writel(value, priv->fpga_base_addr + reg_offset); 146 u32 reg_offset) 148 return __raw_readl(priv->fpga_base_addr + reg_offset); 152 u32 reg_offset, u32 value) 154 __raw_writel(value, priv->fpga_base_addr + reg_offset); 145 socfpga_fpga_raw_readl(struct socfpga_fpga_priv *priv, u32 reg_offset) argument 151 socfpga_fpga_raw_writel(struct socfpga_fpga_priv *priv, u32 reg_offset, u32 value) argument
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/linux-master/drivers/gpu/host1x/hw/ |
H A D | intr_hw.c | 82 u32 reg_offset = id / 32; local 83 u32 irq_index = reg_offset % host->num_syncpt_irqs;
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/linux-master/drivers/phy/rockchip/ |
H A D | phy-rockchip-usb.c | 69 unsigned int reg_offset; member in struct:rockchip_usb_phy 84 return regmap_write(phy->base->reg_base, phy->reg_offset, val); 124 ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val); 205 unsigned int reg_offset; local 217 if (of_property_read_u32(child, "reg", ®_offset)) { 227 rk_phy->reg_offset = reg_offset; 236 if (base->pdata->phys[i].reg == reg_offset) {
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/linux-master/drivers/net/ethernet/wangxun/ngbe/ |
H A D | ngbe_type.h | 85 #define NGBE_PHY_CONFIG(reg_offset) (0x14000 + ((reg_offset) * 4))
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/linux-master/drivers/accel/habanalabs/common/ |
H A D | security.c | 71 * @reg_offset: register offset will be converted to bit offset in pb block 75 static int hl_unset_pb_in_block(struct hl_device *hdev, u32 reg_offset, argument 78 if ((reg_offset >= HL_BLOCK_SIZE) || (reg_offset & 0x3)) { 81 reg_offset, HL_BLOCK_SIZE); 86 (reg_offset & (HL_BLOCK_SIZE - 1)) >> 2); 107 u32 reg_offset; local 115 reg_offset = (mm_reg_addr + offset) - pb_blocks[block_num]; 117 return hl_unset_pb_in_block(hdev, reg_offset, &sgs_array[block_num]); 137 u32 reg_offset; local [all...] |
/linux-master/drivers/soc/qcom/ |
H A D | llcc-qcom.c | 136 const u32 *reg_offset; member in struct:qcom_llcc_config 529 .reg_offset = llcc_v2_1_reg_offset, 536 .reg_offset = llcc_v2_1_reg_offset, 543 .reg_offset = llcc_v2_1_reg_offset, 550 .reg_offset = llcc_v2_1_reg_offset, 560 .reg_offset = llcc_v1_reg_offset, 570 .reg_offset = llcc_v1_reg_offset, 580 .reg_offset = llcc_v1_reg_offset, 590 .reg_offset = llcc_v1_reg_offset, 600 .reg_offset [all...] |
/linux-master/drivers/crypto/cavium/zip/ |
H A D | zip_main.h | 68 u64 reg_offset; member in struct:zip_registers
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