/linux-master/drivers/soc/amlogic/ |
H A D | meson-canvas.c | 36 void __iomem *reg_base; member in struct:meson_canvas 44 writel_relaxed(val, canvas->reg_base + reg); 49 return readl_relaxed(canvas->reg_base + reg); 179 canvas->reg_base = devm_platform_ioremap_resource(pdev, 0); 180 if (IS_ERR(canvas->reg_base)) 181 return PTR_ERR(canvas->reg_base);
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/linux-master/drivers/reset/ |
H A D | reset-meson.c | 26 void __iomem *reg_base; member in struct:meson_reset 39 void __iomem *reg_addr = data->reg_base + (bank << 2); 57 reg_addr = data->reg_base + data->param->level_offset + (bank << 2); 124 data->reg_base = devm_platform_ioremap_resource(pdev, 0); 125 if (IS_ERR(data->reg_base)) 126 return PTR_ERR(data->reg_base);
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/linux-master/drivers/watchdog/ |
H A D | s3c2410_wdt.c | 182 void __iomem *reg_base; member in struct:s3c2410_wdt 428 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 430 writel(wtcon, wdt->reg_base + S3C2410_WTCON); 439 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); 449 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 451 writel(wtcon, wdt->reg_base + S3C2410_WTCON); 476 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 490 writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); 491 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); 492 writel(wtcon, wdt->reg_base [all...] |
/linux-master/drivers/block/ |
H A D | n64cart.c | 32 static u32 __iomem *reg_base; variable 44 writel(value, reg_base + reg); 49 return readl(reg_base + reg); 134 reg_base = devm_platform_ioremap_resource(pdev, 0); 135 if (IS_ERR(reg_base)) 136 return PTR_ERR(reg_base);
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/linux-master/drivers/crypto/marvell/octeontx/ |
H A D | otx_cptvf_main.c | 349 vqx_ctl.u = readq(cptvf->reg_base + OTX_CPT_VQX_CTL(0)); 351 writeq(vqx_ctl.u, cptvf->reg_base + OTX_CPT_VQX_CTL(0)); 358 vqx_dbell.u = readq(cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0)); 360 writeq(vqx_dbell.u, cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0)); 367 vqx_inprg.u = readq(cptvf->reg_base + OTX_CPT_VQX_INPROG(0)); 369 writeq(vqx_inprg.u, cptvf->reg_base + OTX_CPT_VQX_INPROG(0)); 376 vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); 378 writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); 385 vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); 393 vqx_dwait.u = readq(cptvf->reg_base [all...] |
/linux-master/drivers/net/can/sja1000/ |
H A D | sja1000_platform.c | 43 return ioread8(priv->reg_base + reg); 48 iowrite8(val, priv->reg_base + reg); 53 return ioread8(priv->reg_base + reg * 2); 58 iowrite8(val, priv->reg_base + reg * 2); 63 return ioread8(priv->reg_base + reg * 4); 68 iowrite8(val, priv->reg_base + reg * 4); 78 iowrite16(reg, priv->reg_base + 0); 79 val = ioread16(priv->reg_base + 2); 92 iowrite16(reg, priv->reg_base + 0); 93 iowrite16(val, priv->reg_base [all...] |
H A D | sja1000_isa.c | 71 return readb(priv->reg_base + reg); 77 writeb(val, priv->reg_base + reg); 82 return inb((unsigned long)priv->reg_base + reg); 88 outb(val, (unsigned long)priv->reg_base + reg); 94 unsigned long flags, base = (unsigned long)priv->reg_base; 108 unsigned long flags, base = (unsigned long)priv->reg_base; 158 priv->reg_base = base; 163 priv->reg_base = (void __iomem *)port[idx]; 208 dev_info(&pdev->dev, "%s device registered (reg_base=0x%p, irq=%d)\n", 209 DRV_NAME, priv->reg_base, de [all...] |
/linux-master/drivers/clk/samsung/ |
H A D | clk.c | 81 ctx->reg_base = base; 197 ctx->reg_base + list->offset, 221 ctx->reg_base + list->offset, 227 ctx->reg_base + list->offset, list->shift, 249 list->flags, ctx->reg_base + list->offset, 288 samsung_clk_save(reg_cache->reg_base, reg_cache->rdump, 290 samsung_clk_restore(reg_cache->reg_base, reg_cache->rsuspend, 301 samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump, 310 void samsung_clk_extended_sleep_init(void __iomem *reg_base, argument 330 reg_cache->reg_base 373 void __iomem *reg_base; local [all...] |
/linux-master/drivers/net/ethernet/marvell/octeontx2/af/ |
H A D | ptp.h | 17 void __iomem *reg_base; member in struct:ptp
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/linux-master/drivers/gpu/drm/loongson/ |
H A D | lsdc_gfxpll.h | 40 u32 reg_base; member in struct:loongson_gfxpll
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H A D | lsdc_pixpll.h | 73 u32 reg_base; member in struct:lsdc_pixpll
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/linux-master/drivers/misc/mchp_pci1xxxx/ |
H A D | mchp_pci1xxxx_otpe2p.c | 69 void __iomem *reg_base; member in struct:pci1xxxx_otp_eeprom_device 78 void __iomem *sys_lock = priv->reg_base + 92 void __iomem *sys_lock = priv->reg_base + 99 void __iomem *rb = priv->reg_base; 124 void __iomem *rb = priv->reg_base; 166 void __iomem *rb = priv->reg_base; 213 writew(lo, priv->reg_base + MMAP_OTP_OFFSET(OTP_ADDR_LOW_OFFSET)); 214 writew(hi, priv->reg_base + MMAP_OTP_OFFSET(OTP_ADDR_HIGH_OFFSET)); 221 void __iomem *rb = priv->reg_base; 271 void __iomem *rb = priv->reg_base; [all...] |
/linux-master/drivers/crypto/marvell/octeontx2/ |
H A D | otx2_cptvf.h | 12 void __iomem *reg_base; /* Register start address */ member in struct:otx2_cptvf_dev
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/linux-master/drivers/irqchip/ |
H A D | irq-orion.c | 41 u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) & 85 gc->reg_base = ioremap(r.start, resource_size(&r)); 86 if (!gc->reg_base) 94 writel(0, gc->reg_base + ORION_IRQ_MASK); 113 u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) & 182 gc->reg_base = ioremap(r.start, resource_size(&r)); 183 if (!gc->reg_base) { 196 writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK); 197 writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE);
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H A D | irq-uniphier-aidet.c | 25 void __iomem *reg_base; member in struct:uniphier_aidet_priv 37 tmp = readl_relaxed(priv->reg_base + reg); 40 writel_relaxed(tmp, priv->reg_base + reg); 182 priv->reg_base = devm_platform_ioremap_resource(pdev, 0); 183 if (IS_ERR(priv->reg_base)) 184 return PTR_ERR(priv->reg_base); 208 priv->reg_base + UNIPHIER_AIDET_DETCONF + i * 4); 220 priv->reg_base + UNIPHIER_AIDET_DETCONF + i * 4);
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/linux-master/drivers/video/fbdev/ |
H A D | pxa168fb.c | 287 writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV); 297 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); 322 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0); 334 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1); 344 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1); 357 writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0); 369 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL) & 0x00000001; 382 writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL); 395 writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL); 418 x = readl(fbi->reg_base [all...] |
H A D | goldfishfb.c | 38 void __iomem *reg_base; member in struct:goldfish_fb 55 status = readl(fb->reg_base + FB_INT_STATUS); 123 writel(fb->rotation, fb->reg_base + FB_SET_ROTATION); 139 fb->reg_base + FB_SET_BASE); 154 writel(1, fb->reg_base + FB_SET_BLANK); 157 writel(0, fb->reg_base + FB_SET_BLANK); 197 fb->reg_base = ioremap(r->start, PAGE_SIZE); 198 if (fb->reg_base == NULL) { 209 width = readl(fb->reg_base + FB_GET_WIDTH); 210 height = readl(fb->reg_base [all...] |
/linux-master/drivers/dma/ioat/ |
H A D | dma.h | 26 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->ioat_dma->reg_base) / 0x80) 52 * @reg_base: MMIO register space base address 65 void __iomem *reg_base; member in struct:ioatdma_device 97 void __iomem *reg_base; member in struct:ioatdma_chan 242 return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET); 252 return readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 260 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 268 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 276 cmd = readb(ioat_chan->reg_base [all...] |
/linux-master/drivers/gpio/ |
H A D | gpio-hisi.c | 38 void __iomem *reg_base; member in struct:hisi_gpio 48 void __iomem *reg = hisi_gpio->reg_base + off; 58 void __iomem *reg = hisi_gpio->reg_base + off; 284 hisi_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0); 285 if (IS_ERR(hisi_gpio->reg_base)) 286 return PTR_ERR(hisi_gpio->reg_base); 293 hisi_gpio->reg_base + HISI_GPIO_EXT_PORT_WX, 294 hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_SET_WX, 295 hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_CLR_WX, 296 hisi_gpio->reg_base [all...] |
/linux-master/drivers/net/can/ |
H A D | kvaser_pciefd.c | 262 ((pcie)->reg_base + (pcie)->driver_data->address_offset->block) 410 void __iomem *reg_base; member in struct:kvaser_pciefd_can 423 void __iomem *reg_base; member in struct:kvaser_pciefd 514 can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG); 533 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 536 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 547 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 549 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 563 iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 579 mode = ioread32(can->reg_base [all...] |
/linux-master/drivers/crypto/cavium/cpt/ |
H A D | cptvf_main.c | 366 vqx_ctl.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_CTL(0, 0)); 368 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_CTL(0, 0), vqx_ctl.u); 375 vqx_dbell.u = cpt_read_csr64(cptvf->reg_base, 378 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DOORBELL(0, 0), 386 vqx_inprg.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_INPROG(0, 0)); 388 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_INPROG(0, 0), vqx_inprg.u); 395 vqx_dwait.u = cpt_read_csr64(cptvf->reg_base, 398 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAIT(0, 0), 406 vqx_dwait.u = cpt_read_csr64(cptvf->reg_base, 409 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAI [all...] |
/linux-master/drivers/perf/ |
H A D | arm_smmuv3_pmu.c | 132 void __iomem *reg_base; member in struct:smmu_pmu 159 smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL); 160 writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR); 181 writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR); 182 writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL); 196 writel(0xffff, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx)); 224 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0); 229 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0); 234 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0); 240 writeq(BIT(idx), smmu_pmu->reg_base [all...] |
/linux-master/drivers/net/ethernet/stmicro/stmmac/ |
H A D | dwmac-loongson1.c | 55 unsigned long reg_base; local 62 reg_base = (unsigned long)res->start; 64 if (reg_base == LS1B_GMAC0_BASE) { 83 } else if (reg_base == LS1B_GMAC1_BASE) { 109 reg_base);
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/linux-master/drivers/dma/ |
H A D | mmp_tdma.c | 120 void __iomem *reg_base; member in struct:mmp_tdma_chan 145 writel(phys, tdmac->reg_base + TDNDPR); 146 writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND, 147 tdmac->reg_base + TDCR); 153 writel(TDIMR_COMP, tdmac->reg_base + TDIMR); 155 writel(0, tdmac->reg_base + TDIMR); 161 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, 162 tdmac->reg_base + TDCR); 171 tdcr = readl(tdmac->reg_base + TDCR); 174 writel(tdcr, tdmac->reg_base [all...] |
/linux-master/drivers/extcon/ |
H A D | extcon-rtk-type-c.c | 57 void __iomem *reg_base; member in struct:type_c_data 244 void __iomem *reg = type_c->reg_base + USB_TYPEC_CTRL_CC1_0; 369 void __iomem *reg = type_c->reg_base + USB_TYPEC_CTRL; 382 void __iomem *reg = type_c->reg_base + USB_TYPEC_CTRL; 397 void __iomem *reg_base = type_c->reg_base; local 401 default_ctrl = readl(reg_base + USB_TYPEC_CTRL) & DEBOUNCE_TIME_MASK; 402 writel(default_ctrl, reg_base + USB_TYPEC_CTRL); 404 cc1_config = readl(reg_base + USB_TYPEC_CTRL_CC1_0); 405 cc2_config = readl(reg_base 464 void __iomem *reg_base = type_c->reg_base; local [all...] |