Searched refs:intr (Results 76 - 100 of 528) sorted by relevance

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/linux-master/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dtop.h20 int intr; member in struct:nvkm_top_device
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/vfn/
H A Dpriv.h10 const struct nvkm_intr_func *intr; member in struct:nvkm_vfn_func
H A Dga100.c39 .intr = &tu102_vfn_intr,
/linux-master/drivers/mtd/nand/onenand/
H A Donenand_omap2.c129 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr) argument
131 printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
132 msg, state, ctrl, intr);
136 unsigned int intr)
139 "intr 0x%04x\n", msg, state, ctrl, intr);
146 unsigned int intr = 0; local
170 intr = read_reg(c, ONENAND_REG_INTERRUPT);
171 if (intr & ONENAND_INT_MASTER)
176 wait_err("controller error", state, ctrl, intr);
135 wait_warn(char *msg, int state, unsigned int ctrl, unsigned int intr) argument
[all...]
/linux-master/drivers/scsi/
H A Dmac53c94.c46 int intr; member in struct:fsc_state
198 int nb, stat, seq, intr; local
207 intr = readb(&regs->interrupt);
210 printk(KERN_DEBUG "mac53c94_intr, intr=%x stat=%x seq=%x phase=%d\n",
211 intr, stat, seq, state->phase);
214 if (intr & INTR_RESET) {
222 if (intr & INTR_ILL_CMD) {
223 printk(KERN_ERR "53c94: invalid cmd, intr=%x stat=%x seq=%x phase=%d\n",
224 intr, stat, seq, state->phase);
231 printk("53c94: bad error, intr
[all...]
/linux-master/drivers/accel/habanalabs/common/
H A Dirq.c258 struct hl_user_interrupt *intr)
265 ts_free_jobs_data = &intr->ts_free_jobs_data;
283 intr->interrupt_id);
300 timestamp = ktime_to_ns(intr->timestamp);
305 pend, pend->ts_reg_info.timestamp_kernel_addr, intr->interrupt_id);
329 static void handle_user_interrupt_ts_list(struct hl_device *hdev, struct hl_user_interrupt *intr) argument
351 spin_lock_irqsave(&intr->ts_list_lock, flags);
352 list_for_each_entry_safe(pend, temp_pend, &intr->ts_list_head, list_node) {
358 &dynamic_alloc_list_head, intr);
364 spin_unlock_irqrestore(&intr
255 handle_registration_node(struct hl_device *hdev, struct hl_user_pending_interrupt *pend, struct list_head **free_list, struct list_head **dynamic_alloc_list, struct hl_user_interrupt *intr) argument
377 handle_user_interrupt_wait_list(struct hl_device *hdev, struct hl_user_interrupt *intr) argument
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dgt215.c144 u32 intr = nvkm_rd32(device, 0x10a008) & disp & ~(disp >> 16); local
146 if (intr & 0x00000020) {
153 intr &= ~0x00000020;
157 if (intr & 0x00000040) {
160 intr &= ~0x00000040;
163 if (intr & 0x00000080) {
168 intr &= ~0x00000080;
171 if (intr) {
172 nvkm_error(subdev, "intr %08x\n", intr);
[all...]
H A Dgf100.c54 .intr = gt215_pmu_intr,
/linux-master/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmmio.c89 u32 intr, mask = 0, tx_mcu_mask = mt7615_tx_mcu_int_mask(dev); local
94 intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
95 intr &= dev->mt76.mmio.irqmask;
96 mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
98 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
100 mask |= intr & MT_INT_RX_DONE_ALL;
101 if (intr & tx_mcu_mask)
105 if (intr & tx_mcu_mask)
108 if (intr & MT_INT_RX_DONE(0))
111 if (intr
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dgk208.c40 .intr = gk104_runq_intr,
59 .intr = gk104_fifo_intr,
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/fault/
H A Dpriv.h30 void (*intr)(struct nvkm_fault *); member in struct:nvkm_fault_func
38 void (*intr)(struct nvkm_fault_buffer *, bool enable); member in struct:nvkm_fault_func::__anon941
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
H A Dgm107.c77 u32 intr = nvkm_rd32(device, base + 0x00c); local
78 u16 stat = intr & 0x0000ffff;
83 nvkm_error(subdev, "LTC%d_LTS%d: %08x [%s]\n", c, s, intr, msg);
86 nvkm_wr32(device, base + 0x00c, intr);
137 .intr = gm107_ltc_intr,
/linux-master/drivers/gpio/
H A Dgpio-xgs-iproc.c35 void __iomem *intr; member in struct:iproc_gpio_chip
175 int_status = readl_relaxed(chip->intr + IPROC_CCA_INT_STS);
255 chip->intr = devm_platform_ioremap_resource(pdev, 1);
256 if (IS_ERR(chip->intr))
257 return PTR_ERR(chip->intr);
260 val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK);
262 writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK);
298 if (chip->intr) {
301 val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK);
303 writel_relaxed(val, chip->intr
[all...]
/linux-master/drivers/net/wireless/mediatek/mt76/
H A Dmt792x_dma.c32 u32 intr, mask = 0; local
36 intr = mt76_rr(dev, MT_WFDMA0_HOST_INT_STA);
37 intr &= dev->mt76.mmio.irqmask;
38 mt76_wr(dev, MT_WFDMA0_HOST_INT_STA, intr);
40 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
42 mask |= intr & (irq_map->rx.data_complete_mask |
45 if (intr & dev->irq_map->tx.mcu_complete_mask)
48 if (intr & MT_INT_MCU_CMD) {
56 intr |= irq_map->rx.data_complete_mask;
62 if (intr
[all...]
H A Dsdio_txrx.c82 struct mt76s_intr *intr)
90 for (i = 0; i < intr->rx.num[qid]; i++)
91 len += round_up(intr->rx.len[qid][i] + 4, 4);
118 while (i < intr->rx.num[qid] && buf < end) {
152 struct mt76s_intr intr; local
155 ret = sdio->parse_irq(dev, &intr);
159 trace_dev_irq(dev, intr.isr, 0);
161 if (intr.isr & WHIER_RX0_DONE_INT_EN) {
162 ret = mt76s_rx_run_queue(dev, 0, &intr);
169 if (intr
81 mt76s_rx_run_queue(struct mt76_dev *dev, enum mt76_rxq_id qid, struct mt76s_intr *intr) argument
[all...]
/linux-master/drivers/net/ethernet/cisco/enic/
H A Denic.h178 ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX]; member in struct:enic
255 static inline bool enic_is_err_intr(struct enic *enic, int intr) argument
259 return intr == ENIC_LEGACY_ERR_INTR;
261 return intr == enic_msix_err_intr(enic);
268 static inline bool enic_is_notify_intr(struct enic *enic, int intr) argument
272 return intr == ENIC_LEGACY_NOTIFY_INTR;
274 return intr == enic_msix_notify_intr(enic);
/linux-master/drivers/irqchip/
H A Dirq-mxs.c53 void __iomem *intr; member in struct:icoll_priv
75 return icoll_priv.intr + ((d->hwirq >> 2) * 0x10);
92 icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
98 icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
194 icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0;
223 icoll_priv.intr = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0;
233 writel(0, icoll_priv.intr + i);
/linux-master/drivers/net/ethernet/marvell/octeontx2/af/
H A Dmcs_cnf10kb.c219 void cnf10kb_mcs_bbe_intr_handler(struct mcs *mcs, u64 intr, argument
225 if (!(intr & MCS_BBE_INT_MASK))
232 if (!(intr & BIT_ULL(i)))
238 if (intr & 0xFULL)
253 void cnf10kb_mcs_pab_intr_handler(struct mcs *mcs, u64 intr, argument
259 if (!(intr & MCS_PAB_INT_MASK))
266 if (!(intr & BIT_ULL(i)))
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
H A Dgp102.c159 u32 intr = nvkm_falcon_rd32(falcon, 0x008) & disp & ~(disp >> 16); local
161 if (intr & 0x00000040) {
177 intr &= ~0x00000040;
180 if (intr & 0x00000010) {
187 intr &= ~0x00000010;
190 if (intr) {
191 nvkm_error(subdev, "unhandled intr %08x\n", intr);
192 nvkm_falcon_wr32(falcon, 0x004, intr);
223 .intr
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
H A Dnv10.c86 u32 intr = nvkm_rd32(device, 0x001104); local
87 u32 stat = nvkm_rd32(device, 0x001144) & intr;
90 nvkm_wr32(device, 0x001104, intr);
/linux-master/drivers/gpu/drm/ttm/
H A Dttm_execbuf_util.c75 struct list_head *list, bool intr,
91 ret = ttm_bo_reserve(bo, intr, (ticket == NULL), ticket);
115 ret = ttm_bo_reserve_slowpath(bo, intr, ticket);
74 ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket, struct list_head *list, bool intr, struct list_head *dups) argument
/linux-master/drivers/video/fbdev/
H A Dvalkyriefb.h69 struct vpreg intr; member in struct:valkyrie_regs
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv15.c29 .intr = nv10_gr_intr,
H A Dnv17.c29 .intr = nv10_gr_intr,
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
H A Dg94.c55 .intr = nv50_bus_intr,

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