Searched refs:clock (Results 501 - 525 of 1871) sorted by relevance

<<21222324252627282930>>

/linux-master/drivers/clk/ti/
H A D	clk-816x.c	7 #include <dt-bindings/clock/dm816.h> 9 #include "clock.h"
/linux-master/sound/firewire/digi00x/
H A D	digi00x-pcm.c	104 enum snd_dg00x_clock clock; local 116 /* Check current clock source. */ 117 err = snd_dg00x_stream_get_clock(dg00x, &clock); 120 if (clock != SND_DG00X_CLOCK_INTERNAL) { 132 // When source of clock is not internal or any stream is reserved for 135 if ((clock != SND_DG00X_CLOCK_INTERNAL) ||
/linux-master/drivers/gpu/drm/msm/disp/mdp4/
H A D	mdp4_lvds_connector.c	68 requested = 1000 * mode->clock;
/linux-master/arch/arm/mach-omap1/
H A D	Makefile	9 obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
/linux-master/drivers/clk/mediatek/
H A D	clk-mt8183-audio.c	13 #include <dt-bindings/clock/mt8183-clk.h>
H A D	clk-mt8186-cam.c	8 #include <dt-bindings/clock/mt8186-clk.h>
H A D	clk-mt8195-img.c	9 #include <dt-bindings/clock/mt8195-clk.h>
H A D	clk-mt8195-vdec.c	9 #include <dt-bindings/clock/mt8195-clk.h>
H A D	clk-mt8188-img.c	7 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
H A D	clk-mt8186-mm.c	8 #include <dt-bindings/clock/mt8186-clk.h>
H A D	clk-mt8186-vdec.c	13 #include <dt-bindings/clock/mt8186-clk.h>
H A D	clk-mt8188-vdec.c	7 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
H A D	clk-mt2701-mm.c	13 #include <dt-bindings/clock/mt2701-clk.h>
H A D	clk-mt6779-aud.c	15 #include <dt-bindings/clock/mt6779-clk.h>
H A D	clk-mt7622-hif.c	15 #include <dt-bindings/clock/mt7622-clk.h>
H A D	clk-mt7622-eth.c	15 #include <dt-bindings/clock/mt7622-clk.h>
H A D	clk-mt7629-hif.c	15 #include <dt-bindings/clock/mt7629-clk.h>
H A D	clk-mt8167-mm.c	16 #include <dt-bindings/clock/mt8167-clk.h>
H A D	clk-mt8192-cam.c	13 #include <dt-bindings/clock/mt8192-clk.h>
H A D	clk-mt7986-eth.c	15 #include <dt-bindings/clock/mt7986-clk.h>
H A D	clk-mt8192-imp_iic_wrap.c	13 #include <dt-bindings/clock/mt8192-clk.h>
H A D	clk-mt8192-mdp.c	13 #include <dt-bindings/clock/mt8192-clk.h>
H A D	clk-mt8192-vdec.c	13 #include <dt-bindings/clock/mt8192-clk.h>
/linux-master/drivers/gpu/drm/renesas/rcar-du/
H A D	rcar_dw_hdmi.c	46 * The maximum supported clock frequency is 297 MHz, as shown in the PHY 49 if (mode->clock > 297000)
/linux-master/drivers/mmc/host/
H A D	via-sdmmc.c	468 /* It seems that our DMA can not work normally with 375kHz clock */ 725 u8 clock; local 753 if (ios->clock >= 48000000) 754 clock = PCI_CLK_48M; 755 else if (ios->clock >= 33000000) 756 clock = PCI_CLK_33M; 757 else if (ios->clock >= 24000000) 758 clock = PCI_CLK_24M; 759 else if (ios->clock >= 16000000) 760 clock [all...]

Completed in 178 milliseconds

<<21222324252627282930>>

Indexes created Mon May 20 13:24:45 MDT 2024