1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
5 *	   Ryder Lee <ryder.lee@mediatek.com>
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/mod_devicetable.h>
10#include <linux/platform_device.h>
11
12#include "clk-mtk.h"
13#include "clk-gate.h"
14
15#include <dt-bindings/clock/mt7629-clk.h>
16
17#define GATE_PCIE(_id, _name, _parent, _shift)				\
18	GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
19
20#define GATE_SSUSB(_id, _name, _parent, _shift)				\
21	GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
22
23static const struct mtk_gate_regs pcie_cg_regs = {
24	.set_ofs = 0x30,
25	.clr_ofs = 0x30,
26	.sta_ofs = 0x30,
27};
28
29static const struct mtk_gate_regs ssusb_cg_regs = {
30	.set_ofs = 0x30,
31	.clr_ofs = 0x30,
32	.sta_ofs = 0x30,
33};
34
35static const struct mtk_gate ssusb_clks[] = {
36	GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
37		   "to_u2_phy_1p", 0),
38	GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
39	GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
40	GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
41	GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "to_usb3_mcu", 7),
42	GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "to_usb3_dma", 8),
43};
44
45static const struct mtk_gate pcie_clks[] = {
46	GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
47	GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
48	GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "from_top_ahb", 14),
49	GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "from_top_axi", 15),
50	GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
51	GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
52	GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
53	GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
54	GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "from_top_ahb", 20),
55	GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "from_top_axi", 21),
56	GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
57	GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
58};
59
60static u16 rst_ofs[] = { 0x34, };
61
62static const struct mtk_clk_rst_desc clk_rst_desc = {
63	.version = MTK_RST_SIMPLE,
64	.rst_bank_ofs = rst_ofs,
65	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
66};
67
68static const struct mtk_clk_desc ssusb_desc = {
69	.clks = ssusb_clks,
70	.num_clks = ARRAY_SIZE(ssusb_clks),
71	.rst_desc = &clk_rst_desc,
72};
73
74static const struct mtk_clk_desc pcie_desc = {
75	.clks = pcie_clks,
76	.num_clks = ARRAY_SIZE(pcie_clks),
77	.rst_desc = &clk_rst_desc,
78};
79
80static const struct of_device_id of_match_clk_mt7629_hif[] = {
81	{ .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc },
82	{ .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc },
83	{ /* sentinel */ }
84};
85MODULE_DEVICE_TABLE(of, of_match_clk_mt7629_hif);
86
87static struct platform_driver clk_mt7629_hif_drv = {
88	.probe = mtk_clk_simple_probe,
89	.remove_new = mtk_clk_simple_remove,
90	.driver = {
91		.name = "clk-mt7629-hif",
92		.of_match_table = of_match_clk_mt7629_hif,
93	},
94};
95module_platform_driver(clk_mt7629_hif_drv);
96MODULE_LICENSE("GPL");
97