Searched refs:tile (Results 51 - 75 of 138) sorted by relevance

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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv17.c30 .tile = nv10_gr_tile,
H A Dpriv.h23 void (*tile)(struct nvkm_gr *, int region, struct nvkm_fb_tile *); member in struct:nvkm_gr_func
H A Dnv20.c149 nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) argument
159 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
160 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
161 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
164 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
166 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
168 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);
171 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
173 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
312 /* interesting.. the below overwrites some of the tile setu
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/linux-master/drivers/gpu/drm/nouveau/nvkm/core/
H A Dengine.c77 if (engine->func->tile)
78 engine->func->tile(engine, region, &fb->tile.region[region]);
119 for (i = 0; fb && i < fb->tile.regions; i++)
/linux-master/drivers/gpu/drm/xe/
H A Dxe_ttm_vram_mgr.h18 int xe_ttm_vram_mgr_init(struct xe_tile *tile, struct xe_ttm_vram_mgr *mgr);
H A Dxe_device.h59 static inline struct xe_gt *xe_tile_get_gt(struct xe_tile *tile, u8 gt_id) argument
61 if (drm_WARN_ON(&tile_to_xe(tile)->drm, gt_id >= XE_MAX_GT_PER_TILE))
64 return gt_id ? tile->media_gt : tile->primary_gt;
73 * FIXME: This only works for now because multi-tile and standalone
99 * the primary tile. Primarily intended for early tile initialization, display
102 * we'll return the primary GT from the root tile.
107 * Returns the primary gt of the root tile.
128 * FIXME: This only works for now since multi-tile an
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H A Dxe_bo_types.h35 /** @tile: Tile this BO is attached to (kernel BO only) */
36 struct xe_tile *tile; member in struct:xe_bo
H A Dxe_guc_hwconfig.c55 struct xe_tile *tile = gt_to_tile(gt); local
80 bo = xe_managed_bo_create_pin_map(xe, tile, PAGE_ALIGN(size),
H A Dxe_memirq.c120 struct xe_tile *tile = memirq_to_tile(memirq); local
128 bo = xe_bo_create_pin_map(xe, tile, NULL, SZ_4K,
389 struct xe_tile *tile = memirq_to_tile(memirq); local
404 if (gt->tile != tile)
420 memirq_dispatch_guc(memirq, &map, &tile->primary_gt->uc.guc);
423 if (!tile->media_gt)
428 memirq_dispatch_guc(memirq, &map, &tile->media_gt->uc.guc);
H A Dxe_bo.c120 struct xe_tile *tile; local
123 tile = &xe->tiles[mem_type == XE_PL_STOLEN ? 0 : (mem_type - XE_PL_VRAM0)];
124 return tile->migrate;
707 if (bo->tile)
708 migrate = bo->tile->migrate;
1056 xe_ggtt_remove_bo(bo->tile->mem.ggtt, bo);
1204 struct xe_tile *tile, struct dma_resv *resv,
1219 xe_assert(xe, !tile || type == ttm_bo_type_kernel);
1251 bo->tile = tile;
1203 ___xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo, struct xe_tile *tile, struct dma_resv *resv, struct ttm_lru_bulk_move *bulk, size_t size, u16 cpu_caching, enum ttm_bo_type type, u32 flags) argument
1367 __xe_bo_create_locked(struct xe_device *xe, struct xe_tile *tile, struct xe_vm *vm, size_t size, u64 start, u64 end, u16 cpu_caching, enum ttm_bo_type type, u32 flags) argument
1436 xe_bo_create_locked_range(struct xe_device *xe, struct xe_tile *tile, struct xe_vm *vm, size_t size, u64 start, u64 end, enum ttm_bo_type type, u32 flags) argument
1444 xe_bo_create_locked(struct xe_device *xe, struct xe_tile *tile, struct xe_vm *vm, size_t size, enum ttm_bo_type type, u32 flags) argument
1451 xe_bo_create_user(struct xe_device *xe, struct xe_tile *tile, struct xe_vm *vm, size_t size, u16 cpu_caching, enum ttm_bo_type type, u32 flags) argument
1466 xe_bo_create(struct xe_device *xe, struct xe_tile *tile, struct xe_vm *vm, size_t size, enum ttm_bo_type type, u32 flags) argument
1478 xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_tile *tile, struct xe_vm *vm, size_t size, u64 offset, enum ttm_bo_type type, u32 flags) argument
1517 xe_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile, struct xe_vm *vm, size_t size, enum ttm_bo_type type, u32 flags) argument
1524 xe_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile, const void *data, size_t size, enum ttm_bo_type type, u32 flags) argument
1544 xe_managed_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile, size_t size, u32 flags) argument
1561 xe_managed_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile, const void *data, size_t size, u32 flags) argument
1587 xe_managed_bo_reinit_in_vram(struct xe_device *xe, struct xe_tile *tile, struct xe_bo **src) argument
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H A Dxe_gt_pagefault.c69 static bool vma_is_valid(struct xe_tile *tile, struct xe_vma *vma) argument
71 return BIT(tile->id) & vma->tile_present &&
72 !(BIT(tile->id) & vma->tile_invalidated);
132 struct xe_tile *tile = gt_to_tile(gt); local
180 if (vma_is_valid(tile, vma) && !atomic)
203 ret = xe_pf_begin(&exec, vma, atomic, tile->id);
211 fence = __xe_pt_bind_vma(tile, vma, xe_tile_migrate_engine(tile), NULL, 0,
212 vma->tile_present & BIT(tile->id));
228 vma->tile_invalidated &= ~BIT(tile
510 struct xe_tile *tile = gt_to_tile(gt); local
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H A Dxe_bb.c34 struct xe_tile *tile = gt_to_tile(gt); local
47 bb->bo = xe_sa_bo_new(!usm ? tile->mem.kernel_bb_pool : gt->usm.bb_pool,
H A Dxe_gt.h35 struct xe_gt *xe_gt_alloc(struct xe_tile *tile);
H A Dxe_gsc.c120 struct xe_tile *tile = gt_to_tile(gt); local
128 bo = xe_bo_create_pin_map(xe, tile, NULL, GSC_VER_PKT_SZ * 2,
309 struct xe_tile *tile = gt_to_tile(gt); local
317 if (tile->media_gt && (gt != tile->media_gt)) {
369 struct xe_tile *tile = gt_to_tile(gt); local
383 bo = xe_bo_create_pin_map(xe, tile, NULL, SZ_4M,
H A Dxe_huc.c74 struct xe_tile *tile = gt_to_tile(gt); local
81 if (tile->media_gt && (gt != tile->media_gt)) {
110 struct xe_tile *tile = gt_to_tile(huc_to_gt(huc)); local
120 ret = xe_managed_bo_reinit_in_vram(xe, tile, &huc->fw.bo);
H A Dxe_gt.c58 struct xe_gt *xe_gt_alloc(struct xe_tile *tile) argument
62 gt = drmm_kzalloc(&tile_to_xe(tile)->drm, sizeof(*gt), GFP_KERNEL);
66 gt->tile = tile;
450 struct xe_tile *tile = gt_to_tile(gt); local
452 tile->migrate = xe_migrate_init(tile);
453 if (IS_ERR(tile->migrate)) {
454 err = PTR_ERR(tile->migrate);
H A Dxe_ttm_vram_mgr.c360 int xe_ttm_vram_mgr_init(struct xe_tile *tile, struct xe_ttm_vram_mgr *mgr) argument
362 struct xe_device *xe = tile_to_xe(tile);
363 struct xe_mem_region *vram = &tile->mem.vram;
366 return __xe_ttm_vram_mgr_init(xe, mgr, XE_PL_VRAM0 + tile->id,
378 struct xe_tile *tile = &xe->tiles[res->mem_type - XE_PL_VRAM0]; local
415 phys_addr_t phys = cursor.start + tile->mem.vram.io_start;
H A Dxe_gsc_proxy.c402 struct xe_tile *tile = gt_to_tile(gt); local
412 bo = xe_bo_create_pin_map(xe, tile, NULL, GSC_PROXY_CHANNEL_SIZE,
444 struct xe_tile *tile = gt_to_tile(gt); local
445 struct xe_device *xe = tile_to_xe(tile);
454 /* no multi-tile devices with this feature yet */
455 if (tile->id > 0) {
456 xe_gt_err(gt, "unexpected GSC proxy init on tile %u\n", tile->id);
/linux-master/drivers/hid/
H A Dhid-picolcd_fb.c22 * each. Each tile has 8x64 pixel, each data byte representing
23 * a 1-bit wide vertical line of the tile.
25 * The display can be updated at a tile granularity.
89 /* Send a given tile to PicoLCD */
91 int chip, int tile)
114 hid_set_field(report1->field[0], 4, 0xb8 | tile);
127 tdata = vbitmap + (tile * 4 + chip) * 64;
140 /* Translate a single tile*/
142 int chip, int tile)
146 u8 *vdata = vbitmap + (tile *
90 picolcd_fb_send_tile(struct picolcd_data *data, u8 *vbitmap, int chip, int tile) argument
141 picolcd_fb_update_tile(u8 *vbitmap, const u8 *bitmap, int bpp, int chip, int tile) argument
227 int chip, tile, n; local
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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c994 uint32_t *tile, *macrotile; local
996 tile = adev->gfx.config.tile_mode_array;
1013 tile[reg_offset] = 0;
1019 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1023 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1027 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1031 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1035 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1039 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1042 tile[
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/linux-master/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_av1_req_lat_if.c180 * struct vdec_av1_slice_tile_group - info for each tile
181 * @num_tiles: tile number
182 * @tile_size: input size for each tile
183 * @tile_start_offset: tile offset to input buffer
398 * @context_update_tile_id: specifies which tile to use for the CDF update
400 * or the tile sizes are coded
423 * or the tile sizes are coded
451 * @tile: av1 Tile info
490 struct vdec_av1_slice_tile tile; member in struct:vdec_av1_slice_uncompressed_header
638 * @tile
662 struct vdec_av1_slice_mem tile; member in struct:vdec_av1_slice_vsi
718 struct mtk_vcodec_mem tile; member in struct:vdec_av1_slice_instance
1284 struct vdec_av1_slice_tile *tile = &frame->uh.tile; local
1385 struct vdec_av1_slice_tile *tile = &uh->tile; local
1654 struct vdec_av1_slice_tile *tile = &uh->tile; local
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/linux-master/arch/arm/include/debug/
H A Dvexpress.S26 @ - the original A9 core tile (based on ARM Cortex-A9 r0p1)
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dengine.h27 void (*tile)(struct nvkm_engine *, int region, struct nvkm_fb_tile *); member in struct:nvkm_engine_func
/linux-master/drivers/gpu/drm/imx/dcss/
H A Ddcss-dpr.c98 enum dcss_tile_type tile; member in struct:dcss_dpr_ch
197 pix_in_64byte = pix_in_64byte_map[ch->pix_size][ch->tile];
466 ch->tile = TILE_LINEAR;
469 ch->tile = TILE_GPU_STANDARD;
472 ch->tile = TILE_GPU_SUPER;
481 ch->tile = TILE_LINEAR;
489 ch->mode_ctrl |= ((ch->tile << TILE_TYPE_POS) & TILE_TYPE_MASK);
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
H A Dnv31.c113 nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile) argument
118 nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch);
119 nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit);
120 nvkm_wr32(device, 0x00b000 + (i * 0x10), tile->addr);
266 .tile = nv31_mpeg_tile,

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