Searched refs:reg_base (Results 51 - 75 of 407) sorted by relevance

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/linux-master/drivers/clk/visconti/
H A Dpll-tmpv770x.c63 void __iomem *reg_base; local
65 reg_base = of_iomap(np, 0);
66 if (!reg_base)
69 ctx = visconti_init_pll(np, reg_base, TMPV770X_NR_PLL);
71 iounmap(reg_base);
/linux-master/drivers/crypto/marvell/octeontx2/
H A Dotx2_cptlf.h110 void __iomem *reg_base; member in struct:otx2_cptlfs_info
190 otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,
201 otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
222 void __iomem *reg_base = lf->lfs->reg_base; local
232 otx2_cpt_write64(reg_base, blkaddr, slot, OTX2_CPT_LF_CTL, 0x0);
234 inprog = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_INPROG);
236 otx2_cpt_write64(reg_base, blkaddr, slot, OTX2_CPT_LF_INPROG, inprog);
238 qsize = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_Q_SIZE) & 0x7FFF;
240 inst_ptr = otx2_cpt_read64(reg_base, blkadd
417 otx2_cptlf_set_dev_info(struct otx2_cptlfs_info *lfs, struct pci_dev *pdev, void __iomem *reg_base, struct otx2_mbox *mbox, int blkaddr) argument
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H A Dotx2_cptpf_main.c26 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
28 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
33 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
40 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
52 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
54 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
57 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
64 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
75 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_VFFLR_INTX(0),
79 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVU
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/linux-master/drivers/clk/nxp/
H A Dclk-lpc18xx-ccu.c203 void __iomem *reg_base,
215 div->reg = branch->offset + reg_base;
224 branch->gate.reg = branch->offset + reg_base;
247 static void lpc18xx_ccu_register_branch_clks(void __iomem *reg_base, argument
257 lpc18xx_ccu_register_branch_gate_div(&clk_branches[i], reg_base,
268 void __iomem *reg_base; local
271 reg_base = of_iomap(np, 0);
272 if (!reg_base) {
279 iounmap(reg_base);
286 iounmap(reg_base);
202 lpc18xx_ccu_register_branch_gate_div(struct lpc18xx_clk_branch *branch, void __iomem *reg_base, const char *parent) argument
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/linux-master/drivers/clk/samsung/
H A Dclk-exynos4412-isp.c97 samsung_clk_save(ctx->reg_base, exynos4x12_save_isp,
106 samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp,
116 void __iomem *reg_base; local
118 reg_base = devm_platform_ioremap_resource(pdev, 0);
119 if (IS_ERR(reg_base))
120 return PTR_ERR(reg_base);
127 ctx = samsung_clk_init(dev, reg_base, CLKS_NR_ISP);
/linux-master/drivers/media/platform/mediatek/vcodec/decoder/
H A Dmtk_vcodec_dec_hw.c70 void __iomem *vdec_misc_addr = dev->reg_base[VDEC_HW_MISC] +
76 cg_status = readl(dev->reg_base[VDEC_HW_SYS] + VDEC_HW_ACTIVE_ADDR);
168 subdev_dev->reg_base[VDEC_HW_SYS] = main_dev->reg_base[VDEC_HW_SYS];
177 subdev_dev->reg_base[VDEC_HW_MISC] =
179 if (IS_ERR((__force void *)subdev_dev->reg_base[VDEC_HW_MISC])) {
180 ret = PTR_ERR((__force void *)subdev_dev->reg_base[VDEC_HW_MISC]);
/linux-master/drivers/clk/rockchip/
H A Dclk-cpu.c44 * @reg_base: base register for cpu-clock values.
55 void __iomem *reg_base; member in struct:rockchip_cpuclk
87 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);
112 writel(clksel->val, cpuclk->reg_base + clksel->reg);
130 writel(clksel->val, cpuclk->reg_base + clksel->reg);
148 writel(clksel->val, cpuclk->reg_base + clksel->reg);
201 cpuclk->reg_base + reg_data->core_reg[i]);
212 cpuclk->reg_base + reg_data->mux_core_reg);
217 cpuclk->reg_base + reg_data->core_reg[0]);
254 cpuclk->reg_base
300 rockchip_clk_register_cpuclk(const char *name, const char *const *parent_names, u8 num_parents, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates, void __iomem *reg_base, spinlock_t *lock) argument
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H A Dclk-pll.c34 void __iomem *reg_base; member in struct:rockchip_clk_pll
129 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),
144 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
150 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
158 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
218 pll->reg_base + RK3036_PLLCON(0));
226 pll->reg_base + RK3036_PLLCON(1));
229 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
232 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
273 pll->reg_base
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/linux-master/drivers/cpufreq/
H A Dapple-soc-cpufreq.c65 void __iomem *reg_base; member in struct:apple_cpu_priv
112 u64 reg = readq_relaxed(priv->reg_base + APPLE_DVFS_STATUS);
120 u64 reg = readq_relaxed(priv->reg_base + APPLE_DVFS_CMD);
145 if (readq_poll_timeout_atomic(priv->reg_base + APPLE_DVFS_CMD, reg,
156 writeq_relaxed(reg, priv->reg_base + APPLE_DVFS_CMD);
171 void __iomem **reg_base,
191 *reg_base = of_iomap(args.np, 0);
192 if (!*reg_base)
208 void __iomem *reg_base; local
226 ret = apple_soc_cpufreq_find_cluster(policy, &reg_base,
170 apple_soc_cpufreq_find_cluster(struct cpufreq_policy *policy, void __iomem **reg_base, const struct apple_soc_cpufreq_info **info) argument
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/linux-master/drivers/media/rc/
H A Dmeson-ir-tx.c67 void __iomem *reg_base; member in struct:meson_irtx
90 ir->reg_base + IRB_ADDR1);
102 ir->reg_base + IRB_ADDR0);
104 writel(readl(ir->reg_base + IRB_ADDR0) & ~IRB_INIT_HIGH,
105 ir->reg_base + IRB_ADDR0);
107 ir->reg_base + IRB_ADDR3);
108 writel(readl(ir->reg_base + IRB_ADDR0) | IRB_ENABLE,
109 ir->reg_base + IRB_ADDR0);
151 writel(ir->buf[ir->buf_head], ir->reg_base + IRB_ADDR2);
199 writel(readl(ir->reg_base
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/linux-master/arch/sparc/kernel/
H A Dsbus.c214 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; local
224 imap += reg_base;
239 iclr = reg_base + SYSIO_ICLR_SLOT0;
242 iclr = reg_base + SYSIO_ICLR_SLOT1;
245 iclr = reg_base + SYSIO_ICLR_SLOT2;
249 iclr = reg_base + SYSIO_ICLR_SLOT3;
276 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; local
281 afsr_reg = reg_base + SYSIO_UE_AFSR;
282 afar_reg = reg_base + SYSIO_UE_AFAR;
350 unsigned long reg_base local
429 unsigned long afsr_reg, afar_reg, reg_base; local
498 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; local
547 unsigned long regs, reg_base; local
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/linux-master/drivers/crypto/cavium/cpt/
H A Dcptpf_main.c38 grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp));
39 cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp),
42 grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0));
45 grp = cpt_read_csr64(cpt->reg_base,
54 pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0));
55 cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0),
71 pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0));
72 cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0),
85 pf_gx_en = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp));
86 cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_E
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/linux-master/drivers/gpio/
H A Dgpio-brcmstb.c48 void __iomem *reg_base; member in struct:brcmstb_gpio_priv
73 void __iomem *reg_base = bank->parent_priv->reg_base; local
75 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
76 bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
108 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
113 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
153 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
199 iedge_config = bank->gc.read_reg(priv->reg_base +
201 iedge_insensitive = bank->gc.read_reg(priv->reg_base
592 void __iomem *reg_base; local
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/linux-master/drivers/net/ethernet/cavium/common/
H A Dcavium_ptp.c129 writeq(comp, clock->reg_base + PTP_CLOCK_COMP);
217 return readq(clock->reg_base + PTP_CLOCK_HI);
246 clock->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO];
275 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
277 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);
280 writeq(clock_comp, clock->reg_base + PTP_CLOCK_COMP);
292 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
294 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);
321 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
323 writeq(clock_cfg, clock->reg_base
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/linux-master/drivers/crypto/marvell/octeontx/
H A Dotx_cptpf_main.c20 writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1CX(0));
26 writeq(~0ull, cpt->reg_base + OTX_CPT_PF_MBOX_ENA_W1SX(0));
39 writeq(1, cpt->reg_base + OTX_CPT_PF_RESET);
46 pf_cnsts.u = readq(cpt->reg_base + OTX_CPT_PF_CONSTANTS);
55 bist_sts.u = readq(cpt->reg_base + OTX_CPT_PF_BIST_STATUS);
63 bist_sts.u = readq(cpt->reg_base + OTX_CPT_PF_EXE_BIST_STATUS);
222 cpt->reg_base = pci_iomap(pdev, OTX_CPT_PF_PCI_CFG_BAR, 0);
223 if (!cpt->reg_base) {
249 pci_iounmap(pdev, cpt->reg_base);
275 pci_iounmap(pdev, cpt->reg_base);
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/linux-master/drivers/irqchip/
H A Dirq-csky-mpintc.c75 void __iomem *reg_base = this_cpu_read(intcl_reg); local
78 readl_relaxed(reg_base + INTCL_RDYIR));
83 void __iomem *reg_base = this_cpu_read(intcl_reg); local
87 writel_relaxed(d->hwirq, reg_base + INTCL_SENR);
92 void __iomem *reg_base = this_cpu_read(intcl_reg); local
94 writel_relaxed(d->hwirq, reg_base + INTCL_CENR);
99 void __iomem *reg_base = this_cpu_read(intcl_reg); local
101 writel_relaxed(d->hwirq, reg_base + INTCL_CACR);
215 void __iomem *reg_base = this_cpu_read(intcl_reg); local
222 reg_base
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/linux-master/drivers/i2c/busses/
H A Di2c-pca-platform.c29 void __iomem *reg_base; member in struct:i2c_pca_pf_data
42 return ioread8(i2c->reg_base + reg);
48 return ioread8(i2c->reg_base + reg * 2);
54 return ioread8(i2c->reg_base + reg * 4);
60 iowrite8(val, i2c->reg_base + reg);
66 iowrite8(val, i2c->reg_base + reg * 2);
72 iowrite8(val, i2c->reg_base + reg * 4);
149 i2c->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
150 if (IS_ERR(i2c->reg_base))
151 return PTR_ERR(i2c->reg_base);
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H A Di2c-mv64xxx.c127 void __iomem *reg_base; member in struct:mv64xxx_i2c_data
212 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
213 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
214 writel(0, drv_data->reg_base +
216 writel(0, drv_data->reg_base +
220 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
222 drv_data->reg_base + drv_data->reg_offsets.clock);
223 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
224 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
226 drv_data->reg_base
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/linux-master/drivers/clocksource/
H A Dtimer-tegra.c57 void __iomem *reg_base = timer_of_base(to_timer_of(evt)); local
68 writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV);
75 void __iomem *reg_base = timer_of_base(to_timer_of(evt)); local
77 writel_relaxed(0, reg_base + TIMER_PTV);
84 void __iomem *reg_base = timer_of_base(to_timer_of(evt)); local
88 reg_base + TIMER_PTV);
96 void __iomem *reg_base = timer_of_base(to_timer_of(evt)); local
98 writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
106 void __iomem *reg_base = timer_of_base(to_timer_of(evt)); local
108 writel_relaxed(TIMER_PCR_INTR_CLR, reg_base
196 void __iomem *reg_base = timer_of_base(&suspend_rtc_to); local
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/linux-master/drivers/phy/rockchip/
H A Dphy-rockchip-emmc.c86 struct regmap *reg_base; member in struct:rockchip_emmc_phy
106 regmap_write(rk_phy->reg_base,
111 regmap_write(rk_phy->reg_base,
164 regmap_write(rk_phy->reg_base,
177 ret = regmap_read_poll_timeout(rk_phy->reg_base,
187 regmap_write(rk_phy->reg_base,
193 regmap_write(rk_phy->reg_base,
225 ret = regmap_read_poll_timeout(rk_phy->reg_base,
288 regmap_write(rk_phy->reg_base,
295 regmap_write(rk_phy->reg_base,
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H A Dphy-rockchip-pcie.c66 struct regmap *reg_base; member in struct:rockchip_pcie_phy
102 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
110 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
115 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
129 regmap_write(rk_phy->reg_base,
150 regmap_write(rk_phy->reg_base,
178 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
183 regmap_write(rk_phy->reg_base,
198 regmap_read(rk_phy->reg_base,
219 regmap_read(rk_phy->reg_base,
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/linux-master/drivers/input/keyboard/
H A Dnomadik-ske-keypad.c56 * @reg_base: ske registers base address
66 void __iomem *reg_base; member in struct:ske_keypad
82 ret = readl(keypad->reg_base + addr);
85 writel(ret, keypad->reg_base + addr);
101 while ((readl(keypad->reg_base + SKE_RIS) != 0x00000000) && timeout--)
113 value = readl(keypad->reg_base + SKE_DBCR);
116 writel(value, keypad->reg_base + SKE_DBCR);
157 ske_ris = readl(keypad->reg_base + SKE_RIS);
181 ske_asr = readl(keypad->reg_base + SKE_ASR0 + (4 * i));
208 while ((readl(keypad->reg_base
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/linux-master/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp8_if.c144 * @reg_base : HW register base address
158 struct vdec_vp8_hw_reg_base reg_base; member in struct:vdec_vp8_inst
167 void __iomem **reg_base = inst->ctx->dev->reg_base; local
169 inst->reg_base.top = mtk_vcodec_get_reg_addr(reg_base, VDEC_TOP);
170 inst->reg_base.cm = mtk_vcodec_get_reg_addr(reg_base, VDEC_CM);
171 inst->reg_base.hwd = mtk_vcodec_get_reg_addr(reg_base, VDEC_HW
[all...]
/linux-master/drivers/spi/
H A Dspi-pci1xxxx.c160 void __iomem *reg_base; member in struct:pci1xxxx_spi
196 writel(SPI_SYSLOCK, par->reg_base + SPI_SYSLOCK_REG);
197 return readl(par->reg_base + SPI_SYSLOCK_REG);
211 writel(0x0, par->reg_base + SPI_SYSLOCK_REG);
231 regval = readl(spi_bus->reg_base + DEV_REV_REG);
234 regval = readl(spi_bus->reg_base +
309 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
317 writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
388 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
397 writel(regval, par->reg_base
[all...]
/linux-master/drivers/pci/controller/dwc/
H A Dpcie-hisi.c22 void __iomem *reg_base; member in struct:hisi_pcie
68 return pcie->reg_base + where;
102 pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
103 if (!pcie->reg_base)
140 pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
141 if (!pcie->reg_base)

Completed in 277 milliseconds

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