/haiku/src/add-ons/accelerants/nvidia/engine/ |
H A D | nv_bes.c | 24 * si->dm.h_display_start and si->dm.v_display_start determine where the new 47 switch (si->dm.flags & DUALHEAD_BITS) 52 (si->dm.h_display_start + si->dm.timing.h_display)) 65 crtc_hstart = si->dm.h_display_start; 69 crtc_hstart += si->dm.timing.h_display; 73 crtc_hend = crtc_hstart + si->dm.timing.h_display; 74 crtc_vstart = si->dm.v_display_start; 76 crtc_vend = crtc_vstart + si->dm [all...] |
H A D | nv_crtc.c | 47 switch(si->dm.space) 66 drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel; 69 if (si->dm.space != B_RGB32_LITTLE) 770 while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && 983 if (yhigh < (si->dm.timing.v_display - 16)) 1000 while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) &&
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H A D | nv_crtc2.c | 47 switch(si->dm.space) 66 drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel; 69 if (si->dm.space != B_RGB32_LITTLE) 750 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) &&
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/haiku/src/add-ons/accelerants/matrox/engine/ |
H A D | mga_bes.c | 25 * si->dm.h_display_start and si->dm.v_display_start determine where the new 47 crtc_hstart = si->dm.h_display_start; 51 crtc_hstart += si->dm.timing.h_display; 54 crtc_hend = crtc_hstart + si->dm.timing.h_display; 55 crtc_vstart = si->dm.v_display_start; 57 crtc_vend = crtc_vstart + si->dm.timing.v_display; 336 while ((uint16)CR1R(VCOUNT) > (si->dm.timing.v_total - 200)) snooze(4); 390 LOG(4,("Overlay: pixelclock is %dkHz, ", si->dm.timing.pixel_clock)); 391 if (si->dm [all...] |
H A D | mga_crtc.c | 460 tpixclk = 1000000 / si->dm.timing.pixel_clock; 476 refresh = ((si->dm.timing.pixel_clock * 1000) / 477 ((uint32)si->dm.timing.h_total * (uint32)si->dm.timing.v_total)); 487 if ((si->dm.timing.v_display > 768) && (hiprilvl > 3)) hiprilvl = 3; 488 if ((si->dm.timing.v_display > 864) && (hiprilvl > 2) && (refresh >= 76.0)) hiprilvl = 2; 489 if ((si->dm.timing.v_display > 1024) && (hiprilvl > 2)) hiprilvl = 2; 587 if ((si->ps.card_type < G100) && (si->dm.timing.h_total > 2048))
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H A D | mga_acc.c | 65 switch(si->dm.space) 171 switch (si->dm.space) 198 ACCW(YBOT,((si->dm.virtual_height - 1) * 392 if ((si->dm.space == B_CMAP8) || si->ps.sdram) 428 if ((si->dm.space == B_CMAP8) || si->ps.sdram)
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/haiku/src/add-ons/kernel/drivers/graphics/et6x00/ |
H A D | driver.c | 676 ET6000DisplayMode *dm = (ET6000DisplayMode *)buf; local 677 if(dm->magic == ET6000_PRIVATE_DATA_MAGIC) { 678 result = et6000ProposeMode(&dm->mode, dm->memSize); 683 ET6000DisplayMode *dm = (ET6000DisplayMode *)buf; local 684 if(dm->magic == ET6000_PRIVATE_DATA_MAGIC) { 685 result = et6000SetMode(&dm->mode, dm->pciConfigSpace);
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/haiku/src/add-ons/accelerants/matrox/ |
H A D | GetAccelerantHook.c | 226 ((si->fbc.bytes_per_row * si->dm.virtual_height) > (16 * 1024 * 1024)))
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H A D | ProposeDisplayMode.c | 464 status_t GET_MODE_LIST(display_mode *dm) argument 468 memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));
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/haiku/src/add-ons/accelerants/s3/ |
H A D | accel.h | 95 status_t GetModeList(display_mode* dm); 100 status_t GetPixelClockLimits(display_mode* dm, uint32* low, uint32* high);
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/haiku/headers/private/graphics/matrox/ |
H A D | DriverInterface.h | 156 display_mode dm; /* current display mode configuration: head1 */ member in struct:__anon785
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/haiku/headers/private/graphics/neomagic/ |
H A D | DriverInterface.h | 153 display_mode dm; /* current display mode configuration: head1 */ member in struct:__anon799
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/haiku/src/add-ons/accelerants/nvidia/ |
H A D | GetAccelerantHook.c | 222 if (!si->settings.dma_acc || (si->dm.space == B_CMAP8))
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H A D | ProposeDisplayMode.c | 180 SET_DISPLAY_MODE(&si->dm); 572 GET_MODE_LIST(display_mode *dm) argument 576 memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));
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/haiku/src/add-ons/accelerants/skeleton/engine/ |
H A D | acc.c | 37 switch(si->dm.space)
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H A D | crtc.c | 613 while (((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && 806 if (yhigh < (si->dm.timing.v_display - 16)) 818 while ((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display)
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H A D | crtc2.c | 595 while (((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && 768 if (yhigh < (si->dm.timing.v_display - 16)) 780 while ((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display)
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/haiku/src/add-ons/accelerants/via/engine/ |
H A D | acc.c | 37 switch(si->dm.space)
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H A D | crtc2.c | 595 while (((ENG_REG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && 768 if (yhigh < (si->dm.timing.v_display - 16)) 780 while ((ENG_REG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display)
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/haiku/src/add-ons/accelerants/neomagic/engine/ |
H A D | nm_bes.c | 13 * si->dm.h_display_start and si->dm.v_display_start determine where the new 37 crtc_hstart = si->dm.h_display_start; 39 crtc_hend = crtc_hstart + si->dm.timing.h_display; 40 crtc_vstart = si->dm.v_display_start; 42 crtc_vend = crtc_vstart + si->dm.timing.v_display;
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/haiku/src/add-ons/accelerants/intel_extreme/ |
H A D | accelerant_protos.h | 33 status_t intel_get_mode_list(display_mode* dm);
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/haiku/src/add-ons/accelerants/neomagic/ |
H A D | ProposeDisplayMode.c | 332 status_t GET_MODE_LIST(display_mode *dm) argument 336 memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));
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/haiku/src/add-ons/accelerants/skeleton/ |
H A D | ProposeDisplayMode.c | 513 status_t GET_MODE_LIST(display_mode *dm) argument 517 memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));
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/haiku/src/add-ons/accelerants/via/ |
H A D | ProposeDisplayMode.c | 515 status_t GET_MODE_LIST(display_mode *dm) argument 519 memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));
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/haiku/headers/private/graphics/skeleton/ |
H A D | DriverInterface.h | 157 display_mode dm; /* current display mode configuration: head1 */ member in struct:__anon937
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