Searched refs:controller (Results 51 - 75 of 629) sorted by relevance

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/linux-master/scripts/dtc/include-prefixes/arm/intel/pxa/
H A DMakefile4 pxa300-raumfeld-controller.dtb \
/linux-master/drivers/mtd/nand/raw/
H A Dinternals.h8 * NAND controller drivers should not include this file.
117 if (!chip->controller || !chip->controller->ops ||
118 !chip->controller->ops->exec_op)
130 return chip->controller->ops->exec_op(chip, op, true);
142 return chip->controller->ops->exec_op(chip, op, false);
147 if (!chip->controller || !chip->controller->ops ||
148 !chip->controller->ops->setup_interface)
H A DMakefile54 obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o
55 obj-$(CONFIG_MTD_NAND_ARASAN) += arasan-nand-controller.o
56 obj-$(CONFIG_MTD_NAND_INTEL_LGM) += intel-nand-controller.o
57 obj-$(CONFIG_MTD_NAND_ROCKCHIP) += rockchip-nand-controller.o
58 obj-$(CONFIG_MTD_NAND_PL35X) += pl35x-nand-controller.o
59 obj-$(CONFIG_MTD_NAND_RENESAS) += renesas-nand-controller.o
/linux-master/drivers/mailbox/
H A Dstm32-ipcc.c50 struct mbox_controller controller; member in struct:stm32_ipcc
85 struct device *dev = ipcc->controller.dev;
104 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
118 struct device *dev = ipcc->controller.dev;
138 mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
150 controller);
152 dev_dbg(ipcc->controller.dev, "%s: chan:%lu\n", __func__, chan);
169 controller);
174 dev_err(ipcc->controller.dev, "can not enable the clock\n");
189 controller);
[all...]
H A Dhi3660-mailbox.c62 * struct hi3660_mbox - Hi3660 mailbox controller data
65 * @chan: Representation of channels in mailbox controller
67 * @controller: Representation of a communication channel controller
69 * Mailbox controller includes 32 channels and can allocate
77 struct mbox_controller controller; member in struct:hi3660_mbox
82 return container_of(mbox, struct hi3660_mbox, controller);
211 static struct mbox_chan *hi3660_mbox_xlate(struct mbox_controller *controller, argument
214 struct hi3660_mbox *mbox = to_hi3660_mbox(controller);
254 mbox->controller
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H A Dhi6220-mailbox.c87 struct mbox_controller controller; member in struct:hi6220_mbox
223 static struct mbox_chan *hi6220_mbox_xlate(struct mbox_controller *controller, argument
226 struct hi6220_mbox *mbox = dev_get_drvdata(controller->dev);
310 mbox->controller.dev = dev;
311 mbox->controller.chans = &mbox->chan[0];
312 mbox->controller.num_chans = mbox->chan_num;
313 mbox->controller.ops = &hi6220_mbox_ops;
314 mbox->controller.of_xlate = hi6220_mbox_xlate;
332 mbox->controller.txdone_irq = true;
334 mbox->controller
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H A Dsun6i-msgbox.c44 #define mbox_dbg(mbox, ...) dev_dbg((mbox)->controller.dev, __VA_ARGS__)
47 struct mbox_controller controller; member in struct:sun6i_msgbox
80 struct mbox_chan *chan = &mbox->controller.chans[n];
265 mbox->controller.dev = dev;
266 mbox->controller.ops = &sun6i_msgbox_chan_ops;
267 mbox->controller.chans = chans;
268 mbox->controller.num_chans = NUM_CHANS;
269 mbox->controller.txdone_irq = false;
270 mbox->controller.txdone_poll = true;
271 mbox->controller
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/linux-master/drivers/clk/mmp/
H A Dreset.h5 #include <linux/reset-controller.h>
/linux-master/drivers/clk/sunxi-ng/
H A Dccu_reset.h9 #include <linux/reset-controller.h>
/linux-master/drivers/clk/visconti/
H A Dreset.h3 * Toshiba ARM SoC reset controller driver
13 #include <linux/reset-controller.h>
/linux-master/drivers/clk/meson/
H A Dmeson-aoclk.h17 #include <linux/reset-controller.h>
/linux-master/drivers/pci/hotplug/
H A Dpciehp_core.c51 static int init_slot(struct controller *ctrl)
90 static void cleanup_slot(struct controller *ctrl)
103 struct controller *ctrl = to_ctrl(hotplug_slot);
119 struct controller *ctrl = to_ctrl(hotplug_slot);
130 struct controller *ctrl = to_ctrl(hotplug_slot);
141 struct controller *ctrl = to_ctrl(hotplug_slot);
157 * @ctrl: controller to check
166 static void pciehp_check_presence(struct controller *ctrl)
187 struct controller *ctrl;
246 struct controller *ctr
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H A Dpciehp_hpc.c49 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
58 static inline int pciehp_request_irq(struct controller *ctrl)
73 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
78 static inline void pciehp_free_irq(struct controller *ctrl)
86 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
112 static void pcie_wait_cmd(struct controller *ctrl)
121 * If the controller does not generate notifications for command
157 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
208 * pcie_write_cmd - Issue controller command
209 * @ctrl: controller t
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H A Dshpchp.h74 struct controller *ctrl;
90 struct controller { struct
158 int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
159 void shpchp_remove_ctrl_files(struct controller *ctrl);
162 u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
163 u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
164 u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
165 u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
168 void cleanup_slots(struct controller *ctrl);
170 int shpc_init(struct controller *ctr
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H A Dcpqphp.h138 /* offsets to the controller registers based on the above structure layout */
261 struct controller *ctrl;
277 struct controller { struct
278 struct controller *next;
281 void __iomem *hpc_reg; /* cookie for our pci controller location */
293 u8 bus; /* bus number for the pci hotplug controller */
382 #define msg_HPC_rev_error "Unsupported revision of the PCI hot plug controller found.\n"
383 #define msg_HPC_non_compaq_or_intel "The PCI hot plug controller is not supported by this driver.\n"
392 /* debugfs functions for the hotplug controller info */
395 void cpqhp_create_debugfs_files(struct controller *ctr
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/linux-master/drivers/usb/host/
H A Dohci-dbg.c101 ohci_dump_status (struct ohci_hcd *controller, char **next, unsigned *size) argument
103 struct ohci_regs __iomem *regs = controller->regs;
106 temp = ohci_readl (controller, &regs->revision) & 0xff;
107 ohci_dbg_sw (controller, next, size,
111 rh_state_string(controller));
113 temp = ohci_readl (controller, &regs->control);
114 ohci_dbg_sw (controller, next, size,
128 temp = ohci_readl (controller, &regs->cmdstatus);
129 ohci_dbg_sw (controller, next, size,
138 ohci_dump_intr_mask (controller, "intrstatu
191 ohci_dump_roothub( struct ohci_hcd *controller, int verbose, char **next, unsigned *size) argument
240 ohci_dump(struct ohci_hcd *controller) argument
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H A Dehci-xilinx-of.c24 * @hcd: Pointer to the usb_hcd device to which the host controller bound
28 * controller does support LS devices. And in an HS only configuration, it
32 * There are cases when the host controller fails to enable the port due to,
40 dev_warn(hcd->self.controller, "port %d cannot be enabled\n", portnum);
42 dev_warn(hcd->self.controller,
45 dev_warn(hcd->self.controller,
48 dev_warn(hcd->self.controller,
50 dev_warn(hcd->self.controller,
51 "The USB host controller does not support full speed nor low speed devices\n");
52 dev_warn(hcd->self.controller,
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/linux-master/drivers/net/ethernet/mellanox/mlx5/core/sf/
H A Dhw_table.c40 mlx5_sf_controller_to_hwc(struct mlx5_core_dev *dev, u32 controller) argument
42 int idx = !!controller;
47 u16 mlx5_sf_sw_to_hw_id(struct mlx5_core_dev *dev, u32 controller, u16 sw_id) argument
51 hwc = mlx5_sf_controller_to_hwc(dev, controller);
74 static int mlx5_sf_hw_table_id_alloc(struct mlx5_sf_hw_table *table, u32 controller, argument
81 hwc = mlx5_sf_controller_to_hwc(table->dev, controller);
103 static void mlx5_sf_hw_table_id_free(struct mlx5_sf_hw_table *table, u32 controller, int id) argument
107 hwc = mlx5_sf_controller_to_hwc(table->dev, controller);
112 int mlx5_sf_hw_table_sf_alloc(struct mlx5_core_dev *dev, u32 controller, u32 usr_sfnum) argument
123 sw_id = mlx5_sf_hw_table_id_alloc(table, controller, usr_sfnu
160 mlx5_sf_hw_table_sf_free(struct mlx5_core_dev *dev, u32 controller, u16 id) argument
181 mlx5_sf_hw_table_sf_deferred_free(struct mlx5_core_dev *dev, u32 controller, u16 id) argument
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H A Ddevlink.c17 u32 controller; member in struct:mlx5_sf
57 u32 controller, u32 sfnum, struct netlink_ext_ack *extack)
65 if (!mlx5_esw_offloads_controller_valid(esw, controller)) {
66 NL_SET_ERR_MSG_MOD(extack, "Invalid controller number");
70 id_err = mlx5_sf_hw_table_sf_alloc(table->dev, controller, sfnum);
82 hw_fn_id = mlx5_sf_sw_to_hw_id(table->dev, controller, sf->id);
87 sf->controller = controller;
98 mlx5_sf_hw_table_sf_free(table->dev, controller, id_err);
107 mlx5_sf_hw_table_sf_free(table->dev, sf->controller, s
56 mlx5_sf_alloc(struct mlx5_sf_table *table, struct mlx5_eswitch *esw, u32 controller, u32 sfnum, struct netlink_ext_ack *extack) argument
[all...]
/linux-master/drivers/peci/
H A Ddevice.c13 * a result of controller being removed.
116 static int peci_detect(struct peci_controller *controller, u8 addr) argument
126 mutex_lock(&controller->bus_lock);
127 ret = controller->ops->xfer(controller, addr, &req);
128 mutex_unlock(&controller->bus_lock);
149 int peci_device_create(struct peci_controller *controller, u8 addr) argument
158 ret = device_for_each_child(&controller->dev, &addr, peci_dev_exists);
162 ret = peci_detect(controller, addr);
181 device->dev.parent = &controller
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/linux-master/drivers/spi/
H A Dspi-at91-usart.c321 struct spi_controller *controller = dev_id; local
322 struct at91_usart_spi *aus = spi_controller_get_devdata(controller);
347 struct at91_usart_spi *aus = spi_controller_get_devdata(spi->controller);
480 struct spi_controller *controller; local
500 controller = spi_alloc_host(&pdev->dev, sizeof(*aus));
501 if (!controller)
508 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
509 controller->dev.of_node = pdev->dev.parent->of_node;
510 controller->bits_per_word_mask = SPI_BPW_MASK(8);
511 controller
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H A Dspi-rzv2m-csi.c98 struct spi_controller *controller; member in struct:rzv2m_csi_priv
300 if (spi_controller_is_target(csi->controller)) {
399 struct rzv2m_csi_priv *csi = spi_controller_get_devdata(spi->controller);
417 !!spi_controller_is_target(csi->controller));
502 if (!spi_controller_is_target(csi->controller))
531 static int rzv2m_csi_transfer_one(struct spi_controller *controller, argument
535 struct rzv2m_csi_priv *csi = spi_controller_get_devdata(controller);
545 if (!spi_controller_is_target(csi->controller))
576 struct spi_controller *controller; local
587 controller
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/linux-master/drivers/reset/sti/
H A Dreset-syscfg.h11 #include <linux/reset-controller.h>
15 * reset controller.
38 * Description of a system configuration register based reset controller.
40 * @wait_for_ack: The controller will wait for reset assert and de-assert to
42 * @active_low: Are the resets in this controller active low, i.e. clearing
44 * @nr_channels: The number of reset channels in this controller.
56 * reset controller drivers. This registers a reset
57 * controller configured by the OF match data for
/linux-master/drivers/clk/mvebu/
H A DMakefile15 obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o
17 obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o
/linux-master/drivers/media/common/siano/
H A Dsmsir.h30 u32 controller; member in struct:ir_t

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