Searched refs:base (Results 51 - 75 of 6511) sorted by relevance

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/linux-master/drivers/clk/imx/
H A Dclk-imx31.c53 static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref) argument
58 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL);
59 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL);
60 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL);
61 clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
62 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3);
63 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);
64 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3);
65 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);
66 clk[per_div] = imx_clk_divider("per_div", "upll", base
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H A Dclk-imx8mq.c288 void __iomem *base; local
308 base = devm_of_iomap(dev, np, 0, NULL);
310 if (WARN_ON(IS_ERR(base))) {
311 err = PTR_ERR(base);
315 hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
316 hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
317 hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
318 hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
319 hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
320 hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base
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/linux-master/drivers/scsi/pcmcia/
H A Dnsp_io.h15 static inline void nsp_write(unsigned int base,
18 static inline unsigned char nsp_read(unsigned int base,
30 static inline void nsp_write(unsigned int base, argument
34 outb(val, (base + index));
37 static inline unsigned char nsp_read(unsigned int base, argument
40 return inb(base + index);
75 static inline void nsp_fifo8_read(unsigned int base, argument
80 nsp_multi_read_1(base, FIFODATA, buf, count);
94 static inline void nsp_fifo16_read(unsigned int base, argument
99 nsp_multi_read_2(base, FIFODAT
113 nsp_fifo32_read(unsigned int base, void *buf, unsigned long count) argument
132 nsp_fifo8_write(unsigned int base, void *buf, unsigned long count) argument
150 nsp_fifo16_write(unsigned int base, void *buf, unsigned long count) argument
168 nsp_fifo32_write(unsigned int base, void *buf, unsigned long count) argument
178 nsp_mmio_write(unsigned long base, unsigned int index, unsigned char val) argument
187 nsp_mmio_read(unsigned long base, unsigned int index) argument
197 nsp_mmio_index_read(unsigned long base, unsigned int reg) argument
207 nsp_mmio_index_write(unsigned long base, unsigned int reg, unsigned char val) argument
219 nsp_mmio_multi_read_4(unsigned long base, unsigned int Register, void *buf, unsigned long count) argument
237 nsp_mmio_fifo32_read(unsigned int base, void *buf, unsigned long count) argument
245 nsp_mmio_multi_write_4(unsigned long base, unsigned int Register, void *buf, unsigned long count) argument
263 nsp_mmio_fifo32_write(unsigned int base, void *buf, unsigned long count) argument
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/linux-master/arch/arm/mach-shmobile/
H A Dsetup-r8a7779.c32 void __iomem *base = ioremap(HPBREG_BASE, 0x00100000); local
37 writel(0xffffffff, base + INT2NTSR0);
38 writel(0x3fffffff, base + INT2NTSR1);
41 writel(0xfffffff0, base + INT2SMSKCR0);
42 writel(0xfff7ffff, base + INT2SMSKCR1);
43 writel(0xfffbffdf, base + INT2SMSKCR2);
44 writel(0xbffffffc, base + INT2SMSKCR3);
45 writel(0x003fee3f, base + INT2SMSKCR4);
47 iounmap(base);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dccg.c31 container_of(dccg, struct dcn_dccg, base)
41 dccg_dcn->base.ctx
62 struct dccg *base; local
69 base = &dccg_dcn->base;
70 base->ctx = ctx;
71 base->funcs = &dccg3_funcs;
77 return &dccg_dcn->base;
87 struct dccg *base; local
94 base
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/linux-master/arch/arm/include/asm/
H A Dcti.h42 * @base: mapped virtual address for the cti base
50 void __iomem *base; member in struct:cti
58 * @base: mapped virtual address for the cti base
64 * @base, @irq and @trig_out to cti.
67 void __iomem *base, int irq, int trig_out)
69 cti->base = base;
87 void __iomem *base local
66 cti_init(struct cti *cti, void __iomem *base, int irq, int trig_out) argument
129 void __iomem *base = cti->base; local
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/linux-master/arch/arm/plat-orion/
H A Dpcie.c55 u32 orion_pcie_dev_id(void __iomem *base) argument
57 return readl(base + PCIE_DEV_ID_OFF) >> 16;
60 u32 orion_pcie_rev(void __iomem *base) argument
62 return readl(base + PCIE_DEV_REV_OFF) & 0xff;
65 int orion_pcie_link_up(void __iomem *base) argument
67 return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
70 int __init orion_pcie_x4_mode(void __iomem *base) argument
72 return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE);
75 int orion_pcie_get_local_bus_nr(void __iomem *base) argument
77 u32 stat = readl(base
82 orion_pcie_set_local_bus_nr(void __iomem *base, int nr) argument
92 orion_pcie_reset(void __iomem *base) argument
123 orion_pcie_setup_wins(void __iomem *base) argument
181 orion_pcie_setup(void __iomem *base) argument
208 orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) argument
227 orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) argument
266 orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, u32 devfn, int where, int size, u32 val) argument
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/linux-master/arch/arm/mach-versatile/
H A Dv2m.c13 static void __iomem *base; local
15 if (!base) {
19 base = of_iomap(node, 0);
22 if (WARN_ON(!base))
25 writel(~0, base + SYS_FLAGSCLR);
26 writel(data, base + SYS_FLAGSSET);
/linux-master/arch/m68k/amiga/
H A Dcia.c51 unsigned char cia_set_irq(struct ciabase *base, unsigned char mask) argument
55 old = (base->icr_data |= base->cia->icr);
57 base->icr_data |= mask;
59 base->icr_data &= ~mask;
60 if (base->icr_data & base->icr_mask)
61 amiga_custom.intreq = IF_SETCLR | base->int_mask;
62 return old & base->icr_mask;
69 unsigned char cia_able_irq(struct ciabase *base, unsigne argument
88 struct ciabase *base = dev_id; local
179 cia_init_IRQ(struct ciabase *base) argument
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/linux-master/drivers/phy/mediatek/
H A Dphy-mtk-mipi-csi-0-5.c26 void __iomem *base; member in struct:mtk_mipi_cdphy_port
39 static void mtk_phy_csi_cdphy_ana_eq_tune(void __iomem *base) argument
41 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_IS, 1);
42 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_BW, 1);
43 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_IS, 1);
44 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_BW, 1);
45 mtk_phy_update_field(base + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_IS, 1);
46 mtk_phy_update_field(base + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_BW, 1);
48 mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_IS, 1);
49 mtk_phy_update_field(base
56 mtk_phy_csi_dphy_ana_eq_tune(void __iomem *base) argument
76 void __iomem *base = port->base; local
155 void __iomem *base = port->base; local
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/linux-master/tools/testing/memblock/tests/
H A Dbasic_api.c36 * A simple test that adds a memory block of a specified base address
48 .base = SZ_1G,
55 memblock_add(r.base, r.size);
57 ASSERT_EQ(rgn->base, r.base);
69 * A simple test that adds a memory block of a specified base address, size,
81 .base = SZ_1M,
88 memblock_add_node(r.base, r.size, 1, MEMBLOCK_HOTPLUG);
90 ASSERT_EQ(rgn->base, r.base);
441 phys_addr_t base, size = SZ_64; local
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/linux-master/drivers/phy/qualcomm/
H A Dphy-qcom-apq8064-sata.c87 void __iomem *base = phy->mmio; local
91 writel_relaxed(0x01, base + SATA_PHY_SER_CTRL);
92 writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0);
97 writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
98 writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
99 writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
100 writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
101 writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2);
104 writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG);
105 writel_relaxed(0x00, base
182 void __iomem *base = phy->mmio; local
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/linux-master/include/linux/platform_data/
H A Dsh_mmcif.h91 static inline void sh_mmcif_boot_cmd_send(void __iomem *base, argument
94 sh_mmcif_writel(base, MMCIF_CE_INT, 0);
95 sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
96 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
99 static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask) argument
105 tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
107 sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
115 static inline int sh_mmcif_boot_cmd(void __iomem *base, argument
118 sh_mmcif_boot_cmd_send(base, cmd, arg);
119 return sh_mmcif_boot_cmd_poll(base,
122 sh_mmcif_boot_do_read_single(void __iomem *base, unsigned int block_nr, unsigned long *buf) argument
145 sh_mmcif_boot_do_read(void __iomem *base, unsigned long first_block, unsigned long nr_blocks, void *buf) argument
174 sh_mmcif_boot_init(void __iomem *base) argument
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/linux-master/arch/loongarch/kernel/
H A Dfpu.S29 .macro sc_save_fp base
30 EX fst.d $f0, \base, (0 * FPU_REG_WIDTH)
31 EX fst.d $f1, \base, (1 * FPU_REG_WIDTH)
32 EX fst.d $f2, \base, (2 * FPU_REG_WIDTH)
33 EX fst.d $f3, \base, (3 * FPU_REG_WIDTH)
34 EX fst.d $f4, \base, (4 * FPU_REG_WIDTH)
35 EX fst.d $f5, \base, (5 * FPU_REG_WIDTH)
36 EX fst.d $f6, \base, (6 * FPU_REG_WIDTH)
37 EX fst.d $f7, \base, (7 * FPU_REG_WIDTH)
38 EX fst.d $f8, \base, (
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/linux-master/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi5_core.c28 void __iomem *base = core->base; local
43 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
44 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
49 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
53 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
55 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
60 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
67 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADD
107 void __iomem *base = core->base; local
118 void __iomem *base = core->base; local
275 void __iomem *base = core->base; local
337 void __iomem *base = core->base; local
367 void __iomem *base = core->base; local
423 void __iomem *base = core->base; local
485 void __iomem *base = core->base; local
501 void __iomem *base = core->base; local
550 void __iomem *base = core->base; local
622 void __iomem *base = core->base; local
758 void __iomem *base = core->base; local
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/linux-master/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi5_core.c41 void __iomem *base = core->base; local
56 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
57 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
66 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
68 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
73 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
75 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
80 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADD
120 void __iomem *base = core->base; local
130 void __iomem *base = core->base; local
307 void __iomem *base = core->base; local
371 void __iomem *base = core->base; local
409 void __iomem *base = core->base; local
465 void __iomem *base = core->base; local
507 void __iomem *base = core->base; local
523 void __iomem *base = core->base; local
572 void __iomem *base = core->base; local
635 void __iomem *base = core->base; local
771 void __iomem *base = core->base; local
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/linux-master/drivers/gpu/drm/nouveau/
H A Dnv10_fence.h9 struct nouveau_fence_chan base; member in struct:nv10_fence_chan
14 struct nouveau_fence_priv base; member in struct:nv10_fence_priv
/linux-master/drivers/gpu/drm/msm/adreno/
H A Da3xx_gpu.h19 struct adreno_gpu base; member in struct:a3xx_gpu
24 #define to_a3xx_gpu(x) container_of(x, struct a3xx_gpu, base)
H A Da4xx_gpu.h16 struct adreno_gpu base; member in struct:a4xx_gpu
21 #define to_a4xx_gpu(x) container_of(x, struct a4xx_gpu, base)
H A Da2xx_gpu.h16 struct adreno_gpu base; member in struct:a2xx_gpu
20 #define to_a2xx_gpu(x) container_of(x, struct a2xx_gpu, base)
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/pm/
H A Dnv40.h4 #define nv40_pm(p) container_of((p), struct nv40_pm, base)
8 struct nvkm_pm base; member in struct:nv40_pm
/linux-master/drivers/gpu/drm/sun4i/
H A Dsun8i_mixer.h38 #define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0)
39 #define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x))
40 #define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x))
41 #define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x))
42 #define SUN8I_MIXER_BLEND_ROUTE(base) ((base)
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/linux-master/drivers/gpu/drm/i915/
H A Di915_perf_oa_regs.h100 #define GEN12_OACTXCONTROL(base) _MMIO((base) + 0x360)
172 #define GEN12_OAM_MMIO_TRG(base) \
173 _MMIO((base) + GEN12_OAM_MMIO_TRG_OFFSET)
175 #define GEN12_OAM_HEAD_POINTER(base) \
176 _MMIO((base) + GEN12_OAM_HEAD_POINTER_OFFSET)
177 #define GEN12_OAM_TAIL_POINTER(base) \
178 _MMIO((base) + GEN12_OAM_TAIL_POINTER_OFFSET)
179 #define GEN12_OAM_BUFFER(base) \
180 _MMIO((base)
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.h32 container_of(pool, struct dcn315_resource_pool, base)
37 struct resource_pool base; member in struct:dcn315_resource_pool
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.h32 container_of(pool, struct dcn316_resource_pool, base)
37 struct resource_pool base; member in struct:dcn316_resource_pool

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