phy/qualcomm/phy-qcom-apq8064-sata.c

87 	void __iomem *base = phy->mmio;
91 	writel_relaxed(0x01, base + SATA_PHY_SER_CTRL);
92 	writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0);
97 	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
98 	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
99 	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
100 	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
101 	writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2);
104 	writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG);
105 	writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG);
107 	writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0);
108 	writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8);
109 	writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9);
110 	writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10);
111 	writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11);
113 	writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0);
114 	writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1);
115 	writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2);
116 	writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3);
117 	writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4);
119 	writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0);
120 	writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1);
121 	writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2);
122 	writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3);
124 	writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0);
125 	writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1);
127 	writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG);
131 	writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG);
132 	writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2);
135 	ret = poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK);
142 	ret = poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL);
149 	ret = poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL);
156 	writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
157 	writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
158 	writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
160 	writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1);
161 	writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0);
162 	writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1);
163 	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2);
164 	writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0);
165 	writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3);
166 	writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
168 	writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL);
169 	writel_relaxed(0x43, base + SATA_PHY_ALIGNP);
170 	writel_relaxed(0x04, base + SATA_PHY_OOB_TERM);
172 	writel_relaxed(0x01, base + SATA_PHY_EQUAL);
173 	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0);
174 	writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1);
182 	void __iomem *base = phy->mmio;
185 	writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0);
186 	writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1);
189 	writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG);