Searched refs:bank (Results 51 - 75 of 367) sorted by relevance

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/linux-master/drivers/pinctrl/nuvoton/
H A Dpinctrl-npcm7xx.c134 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); local
137 bank->gc.base / bank->gc.ngpio,
138 bank->gc.base,
139 bank->gc.base + bank->gc.ngpio);
141 ioread32(bank->base + NPCM7XX_GP_N_DIN),
142 ioread32(bank->base + NPCM7XX_GP_N_DOUT),
143 ioread32(bank->base + NPCM7XX_GP_N_IEM),
144 ioread32(bank
171 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); local
185 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); local
200 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); local
215 struct npcm7xx_gpio *bank; local
237 struct npcm7xx_gpio *bank = gpiochip_get_data(gc); local
285 struct npcm7xx_gpio *bank = gpiochip_get_data(gc); local
296 struct npcm7xx_gpio *bank = gpiochip_get_data(gc); local
309 struct npcm7xx_gpio *bank = gpiochip_get_data(gc); local
1441 npcm7xx_get_slew_rate(struct npcm7xx_gpio *bank, struct regmap *gcr_regmap, unsigned int pin) argument
1461 npcm7xx_set_slew_rate(struct npcm7xx_gpio *bank, struct regmap *gcr_regmap, unsigned int pin, int arg) argument
1505 struct npcm7xx_gpio *bank = local
1531 struct npcm7xx_gpio *bank = local
1677 struct npcm7xx_gpio *bank = local
1707 struct npcm7xx_gpio *bank = local
1770 struct npcm7xx_gpio *bank = local
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/linux-master/arch/x86/platform/scx200/
H A Dscx200_32.c51 int bank; local
54 for (bank = 0; bank < 2; ++bank)
55 scx200_gpio_shadow[bank] = inl(scx200_gpio_base + 0x10 * bank);
/linux-master/drivers/uio/
H A Duio_fsl_elbc_gpcm.c29 Only the entries reg (to identify bank) and elbc-gpcm-* (initial BR/OR
58 u32 bank; member in struct:fsl_elbc_gpcm
86 struct fsl_lbc_bank *bank = &priv->lbc->bank[priv->bank]; local
90 in_be32(&bank->br));
94 in_be32(&bank->or));
105 struct fsl_lbc_bank *bank = &priv->lbc->bank[priv->bank]; local
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/linux-master/drivers/clk/stm32/
H A Dreset-stm32.c35 int bank = id / (reg_width * BITS_PER_BYTE); local
41 addr = data->membase + (bank * reg_width);
53 reg = readl(data->membase + (bank * reg_width));
60 writel(reg, data->membase + (bank * reg_width));
85 int bank = id / (reg_width * BITS_PER_BYTE); local
89 reg = readl(data->membase + (bank * reg_width));
/linux-master/drivers/hwspinlock/
H A Domap_hwspinlock.c77 struct hwspinlock_device *bank; local
114 bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks),
116 if (!bank)
120 bank->lock[i].priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i;
122 return devm_hwspin_lock_register(&pdev->dev, bank, &omap_hwspinlock_ops,
/linux-master/drivers/gpio/
H A Dgpio-sim.c640 static bool gpio_sim_bank_has_label(struct gpio_sim_bank *bank) argument
642 return bank->label && *bank->label;
646 gpio_sim_bank_get_device(struct gpio_sim_bank *bank) argument
648 return bank->parent;
676 struct gpio_sim_bank *bank = line->parent; local
678 return gpio_sim_bank_get_device(bank);
748 static unsigned int gpio_sim_get_line_names_size(struct gpio_sim_bank *bank) argument
753 list_for_each_entry(line, &bank->line_list, siblings) {
754 if (!line->name || (line->offset >= bank
764 gpio_sim_set_line_names(struct gpio_sim_bank *bank, char **line_names) argument
797 struct gpio_sim_bank *bank; local
873 gpio_sim_make_bank_swnode(struct gpio_sim_bank *bank, struct fwnode_handle *parent) argument
937 struct gpio_sim_bank *bank; local
1073 struct gpio_sim_bank *bank = to_gpio_sim_bank(item); local
1091 struct gpio_sim_bank *bank = to_gpio_sim_bank(item); local
1102 struct gpio_sim_bank *bank = to_gpio_sim_bank(item); local
1126 struct gpio_sim_bank *bank = to_gpio_sim_bank(item); local
1138 struct gpio_sim_bank *bank = to_gpio_sim_bank(item); local
1390 struct gpio_sim_bank *bank = to_gpio_sim_bank(&group->cg_item); local
1421 struct gpio_sim_bank *bank = to_gpio_sim_bank(item); local
1451 struct gpio_sim_bank *bank; local
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H A Dgpio-tegra.c63 unsigned int bank; member in struct:tegra_gpio_bank
113 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, argument
116 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
229 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; local
246 spin_lock_irqsave(&bank->dbc_lock[port], flags);
247 if (bank->dbc_cnt[port] < debounce_ms) {
249 bank->dbc_cnt[port] = debounce_ms;
251 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
304 struct tegra_gpio_bank *bank; local
309 bank
383 struct tegra_gpio_bank *bank = NULL; local
466 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; local
501 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; local
537 struct tegra_gpio_bank *bank; local
689 struct tegra_gpio_bank *bank; local
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H A Dgpio-davinci.c94 int bank = offset / 32; local
97 g = d->regs[bank];
134 int bank = offset / 32; local
136 g = d->regs[bank];
149 int bank = offset / 32; local
151 g = d->regs[bank];
193 int bank, i, ret = 0; local
260 for (bank = 0; bank < nbank; bank
478 unsigned gpio, bank; local
624 u32 bank; local
648 u32 bank; local
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H A Dgpio-npcm-sgpio.c138 const struct npcm_sgpio_bank *bank,
143 return gpio->base + bank->rdata_reg;
145 return gpio->base + bank->wdata_reg;
147 return gpio->base + bank->event_config;
149 return gpio->base + bank->event_status;
159 unsigned int bank = GPIO_BANK(offset); local
161 return &npcm_sgpio_banks[bank];
166 const struct npcm_sgpio_bank **bank,
176 *bank = offset_to_bank(*offset);
232 const struct npcm_sgpio_bank *bank local
137 bank_reg(struct npcm_sgpio *gpio, const struct npcm_sgpio_bank *bank, const enum npcm_sgpio_reg reg) argument
164 npcm_sgpio_irqd_to_data(struct irq_data *d, struct npcm_sgpio **gpio, const struct npcm_sgpio_bank **bank, u8 *bit, unsigned int *offset) argument
250 const struct npcm_sgpio_bank *bank; local
319 const struct npcm_sgpio_bank *bank; local
356 const struct npcm_sgpio_bank *bank; local
382 const struct npcm_sgpio_bank *bank; local
443 const struct npcm_sgpio_bank *bank = &npcm_sgpio_banks[i]; local
482 const struct npcm_sgpio_bank *bank = &npcm_sgpio_banks[i]; local
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H A Dgpio-xgene.c135 unsigned int bank; local
137 for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
138 bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
139 gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset);
148 unsigned int bank; local
150 for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank
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H A Dgpio-bcm-kona.c30 /* The remaining registers are per GPIO bank */
31 #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
32 #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
33 #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
34 #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
35 #define GPIO_INT_STATUS(bank) (
445 struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc); local
560 struct bcm_kona_gpio_bank *bank; local
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H A Dgpio-mt7621.c35 int bank; member in struct:mtk_gc
71 offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
81 offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
201 if (rg->bank != gpio / MTK_BANK_WIDTH)
221 mediatek_gpio_bank_probe(struct device *dev, int bank) argument
228 rg = &mtk->gc_map[bank];
232 rg->bank = bank;
234 dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
235 set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRID
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/linux-master/arch/arm/mach-omap2/
H A Dpowerdomain.h47 * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
48 * bank 1 position. This is true for OMAP3430
86 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
87 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
185 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
186 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
190 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
191 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
192 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
226 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u
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H A Dprm2xxx_3xxx.c111 int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, argument
116 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
124 int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, argument
129 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
137 int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) argument
141 m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
147 int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) argument
151 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
/linux-master/drivers/pinctrl/
H A Dpinctrl-st.c64 * There are two registers cfg0 and cfg1 in this style for each bank.
65 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
275 * of each gpio pin in a GPIO bank.
277 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
278 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
371 struct st_gpio_bank *bank = gpio_range_to_bank(range); local
373 return &bank->pc;
668 static inline void __st_gpio_set(struct st_gpio_bank *bank, argument
672 writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
674 writel(BIT(offset), bank
677 st_gpio_direction(struct st_gpio_bank *bank, unsigned int gpio, unsigned int direction) argument
709 struct st_gpio_bank *bank = gpiochip_get_data(chip); local
716 struct st_gpio_bank *bank = gpiochip_get_data(chip); local
723 struct st_gpio_bank *bank = gpiochip_get_data(chip); local
732 struct st_gpio_bank *bank = gpiochip_get_data(chip); local
916 struct st_gpio_bank *bank = gpio_range_to_bank(range); local
1048 st_pctl_dt_setup_retime_packed(struct st_pinctrl *info, int bank, struct st_pio_control *pc) argument
1084 st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info, int bank, struct st_pio_control *pc) argument
1108 st_pctl_dt_setup_retime(struct st_pinctrl *info, int bank, struct st_pio_control *pc) argument
1121 st_pc_get_value(struct device *dev, struct regmap *regmap, int bank, int data, int lsb, int msb) argument
1133 st_parse_syscfgs(struct st_pinctrl *info, int bank, struct device_node *np) argument
1161 st_pctl_dt_calculate_pin(struct st_pinctrl *info, phandle bank, unsigned int offset) argument
1199 phandle bank; local
1306 struct st_gpio_bank *bank = gpiochip_get_data(gc); local
1315 struct st_gpio_bank *bank = gpiochip_get_data(gc); local
1340 struct st_gpio_bank *bank = gpiochip_get_data(gc); local
1407 __gpio_irq_handler(struct st_gpio_bank *bank) argument
1454 struct st_gpio_bank *bank = gpiochip_get_data(gc); local
1503 struct st_gpio_bank *bank = &info->banks[bank_nr]; local
1601 int i = 0, j = 0, k = 0, bank; local
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H A Dpinctrl-pistachio.c58 #define GPIO_BANK_BASE(bank) (0x200 + 0x24 * (bank))
847 static inline u32 gpio_readl(struct pistachio_gpio_bank *bank, u32 reg) argument
849 return readl(bank->base + reg);
852 static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val, argument
855 writel(val, bank->base + reg);
858 static inline void gpio_mask_writel(struct pistachio_gpio_bank *bank, argument
865 gpio_writel(bank, (0x10000 | val) << bit, reg);
868 static inline void gpio_enable(struct pistachio_gpio_bank *bank, argument
871 gpio_mask_writel(bank, GPIO_BIT_E
874 gpio_disable(struct pistachio_gpio_bank *bank, unsigned offset) argument
1168 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip); local
1178 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip); local
1192 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip); local
1200 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip); local
1211 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip); local
1222 struct pistachio_gpio_bank *bank = irqd_to_bank(data); local
1229 struct pistachio_gpio_bank *bank = irqd_to_bank(data); local
1237 struct pistachio_gpio_bank *bank = irqd_to_bank(data); local
1255 struct pistachio_gpio_bank *bank = irqd_to_bank(data); local
1303 struct pistachio_gpio_bank *bank = gpiochip_get_data(gc); local
1347 struct pistachio_gpio_bank *bank = irqd_to_bank(data); local
1365 struct pistachio_gpio_bank *bank; local
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H A Dpinctrl-equilibrium.c240 ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8,
266 struct eqbr_pin_bank *bank; local
270 bank = &pctl->pin_banks[i];
271 if (pin >= bank->pin_base &&
272 (pin - bank->pin_base) < bank->nr_pins)
273 return bank;
290 struct eqbr_pin_bank *bank; local
295 bank = find_pinbank_via_pin(pctl, pin);
296 if (!bank) {
367 get_gpio_ctrls_via_bank(struct eqbr_pinctrl_drv_data *pctl, struct eqbr_pin_bank *bank) argument
386 struct eqbr_pin_bank *bank; local
450 struct eqbr_pin_bank *bank; local
835 pinbank_init(struct device_node *np, struct eqbr_pinctrl_drv_data *drvdata, struct eqbr_pin_bank *bank, unsigned int id) argument
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/linux-master/drivers/mfd/
H A Dabx500-core.c62 int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg, argument
69 return ops->set_register(dev, bank, reg, value);
75 int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg, argument
82 return ops->get_register(dev, bank, reg, value);
88 int abx500_get_register_page_interruptible(struct device *dev, u8 bank, argument
95 return ops->get_register_page(dev, bank,
102 int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank, argument
109 return ops->mask_and_set_register(dev, bank,
/linux-master/arch/arm/mach-sa1100/
H A Dgeneric.h18 mi->bank[__nr].start = (__start), \
19 mi->bank[__nr].size = (__size)
/linux-master/arch/arm/mach-pxa/
H A Dgeneric.h19 mi->bank[__nr].start = (__start), \
20 mi->bank[__nr].size = (__size)
/linux-master/drivers/media/common/b2c2/
H A Dflexcop-sram.c76 static void flexcop_sram_write(struct adapter *adapter, u32 bank, u32 addr, u8 *buf, u32 len)
82 command = bank | addr | 0x04000000 | (*buf << 0x10);
101 static void flex_sram_read(struct adapter *adapter, u32 bank, u32 addr, u8 *buf, u32 len)
107 command = bank | addr | 0x04008000;
142 u32 bank;
144 bank = 0;
147 bank = (addr & 0x18000) << 0x0d;
152 bank = 0x20000000;
154 bank = 0x10000000;
156 flex_sram_write(adapter, bank, add
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/linux-master/drivers/pinctrl/meson/
H A Dpinctrl-meson.c11 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
14 * The AO bank is special because it belongs to the Always-On power
15 * domain which can't be powered off; the bank also uses a set of
31 * For the pull and GPIO configuration every bank uses a contiguous
64 * meson_get_bank() - find the bank containing a given pin
68 * @bank: the found bank
73 struct meson_bank **bank)
80 *bank = &pc->data->banks[i];
91 * @bank
72 meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, struct meson_bank **bank) argument
97 meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, enum meson_reg_type reg_type, unsigned int *reg, unsigned int *bit) argument
184 struct meson_bank *bank; local
201 struct meson_bank *bank; local
264 struct meson_bank *bank; local
283 struct meson_bank *bank; local
311 struct meson_bank *bank; local
402 struct meson_bank *bank; local
438 struct meson_bank *bank; local
591 struct meson_bank *bank; local
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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_aca.c31 typedef int bank_handler_t(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type, void *data);
58 static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank *bank) argument
62 if (!bank)
69 memcpy(&node->bank, bank, sizeof(*bank));
119 static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, struct aca_bank *bank) argument
127 idx + 1, total, aca_regs[i].name, bank->regs[aca_regs[i].reg_idx]);
136 struct aca_bank bank; local
162 memset(&bank,
177 aca_bank_hwip_is_matched(struct aca_bank *bank, enum aca_hwip_type type) argument
198 aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type) argument
299 aca_generate_bank_report(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type, struct aca_bank_report *report) argument
315 handler_aca_log_bank_error(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type, void *data) argument
335 aca_dispatch_bank(struct aca_handle_manager *mgr, struct aca_bank *bank, enum aca_error_type type, bank_handler_t handler, void *data) argument
360 struct aca_bank *bank; local
700 aca_bank_info_decode(struct aca_bank *bank, struct aca_bank_info *info) argument
724 aca_bank_get_error_code(struct amdgpu_device *adev, struct aca_bank *bank) argument
745 aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank, int *err_codes, int size) argument
787 aca_dump_entry(struct seq_file *m, struct aca_bank *bank, enum aca_error_type type, int idx) argument
809 handler_aca_bank_dump(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type, void *data) argument
[all...]
/linux-master/arch/alpha/kernel/
H A Dsys_ruffian.c184 unsigned long bank_addr, bank, ret = 0; local
189 bank = *(vulp)bank_addr;
192 if (bank & 0x01) {
205 bank = (bank & 0x1e) >> 1;
206 if (bank < ARRAY_SIZE(size))
207 ret = size[bank];
/linux-master/drivers/pinctrl/tegra/
H A Dpinctrl-tegra.c30 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) argument
32 return readl(pmx->regs[bank] + reg);
35 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) argument
37 writel_relaxed(val, pmx->regs[bank] + reg);
39 pmx_readl(pmx, bank, reg);
365 s8 *bank, s32 *reg, s8 *bit, s8 *width)
369 *bank = g->pupd_bank;
375 *bank = g->tri_bank;
381 *bank = g->mux_bank;
387 *bank
361 tegra_pinconf_reg(struct tegra_pmx *pmx, const struct tegra_pingroup *g, enum tegra_pinconf_param param, bool report_err, s8 *bank, s32 *reg, s8 *bit, s8 *width) argument
523 s8 bank, bit, width; local
552 s8 bank, bit, width; local
620 s8 bank, bit, width; local
690 unsigned int bank, reg; local
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