1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Driver for the NVIDIA Tegra pinmux 4 * 5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. 6 * 7 * Derived from code: 8 * Copyright (C) 2010 Google, Inc. 9 * Copyright (C) 2010 NVIDIA Corporation 10 * Copyright (C) 2009-2011 ST-Ericsson AB 11 */ 12 13#include <linux/err.h> 14#include <linux/init.h> 15#include <linux/io.h> 16#include <linux/of.h> 17#include <linux/platform_device.h> 18#include <linux/seq_file.h> 19#include <linux/slab.h> 20 21#include <linux/pinctrl/machine.h> 22#include <linux/pinctrl/pinconf.h> 23#include <linux/pinctrl/pinctrl.h> 24#include <linux/pinctrl/pinmux.h> 25 26#include "../core.h" 27#include "../pinctrl-utils.h" 28#include "pinctrl-tegra.h" 29 30static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) 31{ 32 return readl(pmx->regs[bank] + reg); 33} 34 35static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) 36{ 37 writel_relaxed(val, pmx->regs[bank] + reg); 38 /* make sure pinmux register write completed */ 39 pmx_readl(pmx, bank, reg); 40} 41 42static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 43{ 44 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 45 46 return pmx->soc->ngroups; 47} 48 49static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 50 unsigned group) 51{ 52 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 53 54 return pmx->soc->groups[group].name; 55} 56 57static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 58 unsigned group, 59 const unsigned **pins, 60 unsigned *num_pins) 61{ 62 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 63 64 *pins = pmx->soc->groups[group].pins; 65 *num_pins = pmx->soc->groups[group].npins; 66 67 return 0; 68} 69 70#ifdef CONFIG_DEBUG_FS 71static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, 72 struct seq_file *s, 73 unsigned offset) 74{ 75 seq_printf(s, " %s", dev_name(pctldev->dev)); 76} 77#endif 78 79static const struct cfg_param { 80 const char *property; 81 enum tegra_pinconf_param param; 82} cfg_params[] = { 83 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL}, 84 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE}, 85 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT}, 86 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN}, 87 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, 88 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, 89 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL}, 90 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL}, 91 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, 92 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, 93 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, 94 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH}, 95 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH}, 96 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, 97 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, 98 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE}, 99}; 100 101static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 102 struct device_node *np, 103 struct pinctrl_map **map, 104 unsigned *reserved_maps, 105 unsigned *num_maps) 106{ 107 struct device *dev = pctldev->dev; 108 int ret, i; 109 const char *function; 110 u32 val; 111 unsigned long config; 112 unsigned long *configs = NULL; 113 unsigned num_configs = 0; 114 unsigned reserve; 115 struct property *prop; 116 const char *group; 117 118 ret = of_property_read_string(np, "nvidia,function", &function); 119 if (ret < 0) { 120 /* EINVAL=missing, which is fine since it's optional */ 121 if (ret != -EINVAL) 122 dev_err(dev, 123 "%pOF: could not parse property nvidia,function\n", np); 124 function = NULL; 125 } 126 127 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 128 ret = of_property_read_u32(np, cfg_params[i].property, &val); 129 if (!ret) { 130 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); 131 ret = pinctrl_utils_add_config(pctldev, &configs, 132 &num_configs, config); 133 if (ret < 0) 134 goto exit; 135 /* EINVAL=missing, which is fine since it's optional */ 136 } else if (ret != -EINVAL) { 137 dev_err(dev, "%pOF: could not parse property %s\n", 138 np, cfg_params[i].property); 139 } 140 } 141 142 reserve = 0; 143 if (function != NULL) 144 reserve++; 145 if (num_configs) 146 reserve++; 147 ret = of_property_count_strings(np, "nvidia,pins"); 148 if (ret < 0) { 149 dev_err(dev, "%pOF: could not parse property nvidia,pins\n", np); 150 goto exit; 151 } 152 reserve *= ret; 153 154 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, 155 num_maps, reserve); 156 if (ret < 0) 157 goto exit; 158 159 of_property_for_each_string(np, "nvidia,pins", prop, group) { 160 if (function) { 161 ret = pinctrl_utils_add_map_mux(pctldev, map, 162 reserved_maps, num_maps, group, 163 function); 164 if (ret < 0) 165 goto exit; 166 } 167 168 if (num_configs) { 169 ret = pinctrl_utils_add_map_configs(pctldev, map, 170 reserved_maps, num_maps, group, 171 configs, num_configs, 172 PIN_MAP_TYPE_CONFIGS_GROUP); 173 if (ret < 0) 174 goto exit; 175 } 176 } 177 178 ret = 0; 179 180exit: 181 kfree(configs); 182 return ret; 183} 184 185static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 186 struct device_node *np_config, 187 struct pinctrl_map **map, 188 unsigned *num_maps) 189{ 190 unsigned reserved_maps; 191 struct device_node *np; 192 int ret; 193 194 reserved_maps = 0; 195 *map = NULL; 196 *num_maps = 0; 197 198 for_each_child_of_node(np_config, np) { 199 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map, 200 &reserved_maps, num_maps); 201 if (ret < 0) { 202 pinctrl_utils_free_map(pctldev, *map, 203 *num_maps); 204 of_node_put(np); 205 return ret; 206 } 207 } 208 209 return 0; 210} 211 212static const struct pinctrl_ops tegra_pinctrl_ops = { 213 .get_groups_count = tegra_pinctrl_get_groups_count, 214 .get_group_name = tegra_pinctrl_get_group_name, 215 .get_group_pins = tegra_pinctrl_get_group_pins, 216#ifdef CONFIG_DEBUG_FS 217 .pin_dbg_show = tegra_pinctrl_pin_dbg_show, 218#endif 219 .dt_node_to_map = tegra_pinctrl_dt_node_to_map, 220 .dt_free_map = pinctrl_utils_free_map, 221}; 222 223static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) 224{ 225 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 226 227 return pmx->soc->nfunctions; 228} 229 230static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 231 unsigned function) 232{ 233 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 234 235 return pmx->functions[function].name; 236} 237 238static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, 239 unsigned function, 240 const char * const **groups, 241 unsigned * const num_groups) 242{ 243 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 244 245 *groups = pmx->functions[function].groups; 246 *num_groups = pmx->functions[function].ngroups; 247 248 return 0; 249} 250 251static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev, 252 unsigned function, 253 unsigned group) 254{ 255 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 256 const struct tegra_pingroup *g; 257 int i; 258 u32 val; 259 260 g = &pmx->soc->groups[group]; 261 262 if (WARN_ON(g->mux_reg < 0)) 263 return -EINVAL; 264 265 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { 266 if (g->funcs[i] == function) 267 break; 268 } 269 if (WARN_ON(i == ARRAY_SIZE(g->funcs))) 270 return -EINVAL; 271 272 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 273 val &= ~(0x3 << g->mux_bit); 274 val |= i << g->mux_bit; 275 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); 276 277 return 0; 278} 279 280static const struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctldev, 281 unsigned int offset) 282{ 283 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 284 unsigned int group, num_pins, j; 285 const unsigned int *pins; 286 int ret; 287 288 for (group = 0; group < pmx->soc->ngroups; ++group) { 289 ret = tegra_pinctrl_get_group_pins(pctldev, group, &pins, &num_pins); 290 if (ret < 0) 291 continue; 292 for (j = 0; j < num_pins; j++) { 293 if (offset == pins[j]) 294 return &pmx->soc->groups[group]; 295 } 296 } 297 298 dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset); 299 return NULL; 300} 301 302static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, 303 struct pinctrl_gpio_range *range, 304 unsigned int offset) 305{ 306 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 307 const struct tegra_pingroup *group; 308 u32 value; 309 310 if (!pmx->soc->sfsel_in_mux) 311 return 0; 312 313 group = tegra_pinctrl_get_group(pctldev, offset); 314 315 if (!group) 316 return -EINVAL; 317 318 if (group->mux_reg < 0 || group->sfsel_bit < 0) 319 return -EINVAL; 320 321 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); 322 value &= ~BIT(group->sfsel_bit); 323 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); 324 325 return 0; 326} 327 328static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, 329 struct pinctrl_gpio_range *range, 330 unsigned int offset) 331{ 332 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 333 const struct tegra_pingroup *group; 334 u32 value; 335 336 if (!pmx->soc->sfsel_in_mux) 337 return; 338 339 group = tegra_pinctrl_get_group(pctldev, offset); 340 341 if (!group) 342 return; 343 344 if (group->mux_reg < 0 || group->sfsel_bit < 0) 345 return; 346 347 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); 348 value |= BIT(group->sfsel_bit); 349 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); 350} 351 352static const struct pinmux_ops tegra_pinmux_ops = { 353 .get_functions_count = tegra_pinctrl_get_funcs_count, 354 .get_function_name = tegra_pinctrl_get_func_name, 355 .get_function_groups = tegra_pinctrl_get_func_groups, 356 .set_mux = tegra_pinctrl_set_mux, 357 .gpio_request_enable = tegra_pinctrl_gpio_request_enable, 358 .gpio_disable_free = tegra_pinctrl_gpio_disable_free, 359}; 360 361static int tegra_pinconf_reg(struct tegra_pmx *pmx, 362 const struct tegra_pingroup *g, 363 enum tegra_pinconf_param param, 364 bool report_err, 365 s8 *bank, s32 *reg, s8 *bit, s8 *width) 366{ 367 switch (param) { 368 case TEGRA_PINCONF_PARAM_PULL: 369 *bank = g->pupd_bank; 370 *reg = g->pupd_reg; 371 *bit = g->pupd_bit; 372 *width = 2; 373 break; 374 case TEGRA_PINCONF_PARAM_TRISTATE: 375 *bank = g->tri_bank; 376 *reg = g->tri_reg; 377 *bit = g->tri_bit; 378 *width = 1; 379 break; 380 case TEGRA_PINCONF_PARAM_ENABLE_INPUT: 381 *bank = g->mux_bank; 382 *reg = g->mux_reg; 383 *bit = g->einput_bit; 384 *width = 1; 385 break; 386 case TEGRA_PINCONF_PARAM_OPEN_DRAIN: 387 *bank = g->mux_bank; 388 *reg = g->mux_reg; 389 *bit = g->odrain_bit; 390 *width = 1; 391 break; 392 case TEGRA_PINCONF_PARAM_LOCK: 393 *bank = g->mux_bank; 394 *reg = g->mux_reg; 395 *bit = g->lock_bit; 396 *width = 1; 397 break; 398 case TEGRA_PINCONF_PARAM_IORESET: 399 *bank = g->mux_bank; 400 *reg = g->mux_reg; 401 *bit = g->ioreset_bit; 402 *width = 1; 403 break; 404 case TEGRA_PINCONF_PARAM_RCV_SEL: 405 *bank = g->mux_bank; 406 *reg = g->mux_reg; 407 *bit = g->rcv_sel_bit; 408 *width = 1; 409 break; 410 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE: 411 if (pmx->soc->hsm_in_mux) { 412 *bank = g->mux_bank; 413 *reg = g->mux_reg; 414 } else { 415 *bank = g->drv_bank; 416 *reg = g->drv_reg; 417 } 418 *bit = g->hsm_bit; 419 *width = 1; 420 break; 421 case TEGRA_PINCONF_PARAM_SCHMITT: 422 if (pmx->soc->schmitt_in_mux) { 423 *bank = g->mux_bank; 424 *reg = g->mux_reg; 425 } else { 426 *bank = g->drv_bank; 427 *reg = g->drv_reg; 428 } 429 *bit = g->schmitt_bit; 430 *width = 1; 431 break; 432 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE: 433 *bank = g->drv_bank; 434 *reg = g->drv_reg; 435 *bit = g->lpmd_bit; 436 *width = 2; 437 break; 438 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH: 439 *bank = g->drv_bank; 440 *reg = g->drv_reg; 441 *bit = g->drvdn_bit; 442 *width = g->drvdn_width; 443 break; 444 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH: 445 *bank = g->drv_bank; 446 *reg = g->drv_reg; 447 *bit = g->drvup_bit; 448 *width = g->drvup_width; 449 break; 450 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING: 451 *bank = g->drv_bank; 452 *reg = g->drv_reg; 453 *bit = g->slwf_bit; 454 *width = g->slwf_width; 455 break; 456 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING: 457 *bank = g->drv_bank; 458 *reg = g->drv_reg; 459 *bit = g->slwr_bit; 460 *width = g->slwr_width; 461 break; 462 case TEGRA_PINCONF_PARAM_DRIVE_TYPE: 463 if (pmx->soc->drvtype_in_mux) { 464 *bank = g->mux_bank; 465 *reg = g->mux_reg; 466 } else { 467 *bank = g->drv_bank; 468 *reg = g->drv_reg; 469 } 470 *bit = g->drvtype_bit; 471 *width = 2; 472 break; 473 default: 474 dev_err(pmx->dev, "Invalid config param %04x\n", param); 475 return -ENOTSUPP; 476 } 477 478 if (*reg < 0 || *bit < 0) { 479 if (report_err) { 480 const char *prop = "unknown"; 481 int i; 482 483 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 484 if (cfg_params[i].param == param) { 485 prop = cfg_params[i].property; 486 break; 487 } 488 } 489 490 dev_err(pmx->dev, 491 "Config param %04x (%s) not supported on group %s\n", 492 param, prop, g->name); 493 } 494 return -ENOTSUPP; 495 } 496 497 return 0; 498} 499 500static int tegra_pinconf_get(struct pinctrl_dev *pctldev, 501 unsigned pin, unsigned long *config) 502{ 503 dev_err(pctldev->dev, "pin_config_get op not supported\n"); 504 return -ENOTSUPP; 505} 506 507static int tegra_pinconf_set(struct pinctrl_dev *pctldev, 508 unsigned pin, unsigned long *configs, 509 unsigned num_configs) 510{ 511 dev_err(pctldev->dev, "pin_config_set op not supported\n"); 512 return -ENOTSUPP; 513} 514 515static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, 516 unsigned group, unsigned long *config) 517{ 518 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 519 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config); 520 u16 arg; 521 const struct tegra_pingroup *g; 522 int ret; 523 s8 bank, bit, width; 524 s32 reg; 525 u32 val, mask; 526 527 g = &pmx->soc->groups[group]; 528 529 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, 530 &width); 531 if (ret < 0) 532 return ret; 533 534 val = pmx_readl(pmx, bank, reg); 535 mask = (1 << width) - 1; 536 arg = (val >> bit) & mask; 537 538 *config = TEGRA_PINCONF_PACK(param, arg); 539 540 return 0; 541} 542 543static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, 544 unsigned group, unsigned long *configs, 545 unsigned num_configs) 546{ 547 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 548 enum tegra_pinconf_param param; 549 u16 arg; 550 const struct tegra_pingroup *g; 551 int ret, i; 552 s8 bank, bit, width; 553 s32 reg; 554 u32 val, mask; 555 556 g = &pmx->soc->groups[group]; 557 558 for (i = 0; i < num_configs; i++) { 559 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]); 560 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]); 561 562 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, 563 &width); 564 if (ret < 0) 565 return ret; 566 567 val = pmx_readl(pmx, bank, reg); 568 569 /* LOCK can't be cleared */ 570 if (param == TEGRA_PINCONF_PARAM_LOCK) { 571 if ((val & BIT(bit)) && !arg) { 572 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); 573 return -EINVAL; 574 } 575 } 576 577 /* Special-case Boolean values; allow any non-zero as true */ 578 if (width == 1) 579 arg = !!arg; 580 581 /* Range-check user-supplied value */ 582 mask = (1 << width) - 1; 583 if (arg & ~mask) { 584 dev_err(pctldev->dev, 585 "config %lx: %x too big for %d bit register\n", 586 configs[i], arg, width); 587 return -EINVAL; 588 } 589 590 /* Update register */ 591 val &= ~(mask << bit); 592 val |= arg << bit; 593 pmx_writel(pmx, val, bank, reg); 594 } /* for each config */ 595 596 return 0; 597} 598 599#ifdef CONFIG_DEBUG_FS 600static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, 601 struct seq_file *s, unsigned offset) 602{ 603} 604 605static const char *strip_prefix(const char *s) 606{ 607 const char *comma = strchr(s, ','); 608 if (!comma) 609 return s; 610 611 return comma + 1; 612} 613 614static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 615 struct seq_file *s, unsigned group) 616{ 617 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 618 const struct tegra_pingroup *g; 619 int i, ret; 620 s8 bank, bit, width; 621 s32 reg; 622 u32 val; 623 624 g = &pmx->soc->groups[group]; 625 626 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 627 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false, 628 &bank, ®, &bit, &width); 629 if (ret < 0) 630 continue; 631 632 val = pmx_readl(pmx, bank, reg); 633 val >>= bit; 634 val &= (1 << width) - 1; 635 636 seq_printf(s, "\n\t%s=%u", 637 strip_prefix(cfg_params[i].property), val); 638 } 639 640 if (g->mux_reg >= 0) { 641 /* read pinmux function and dump to seq_file */ 642 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 643 val = g->funcs[(val >> g->mux_bit) & 0x3]; 644 645 seq_printf(s, "\n\tfunction=%s", pmx->functions[val].name); 646 } 647} 648 649static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, 650 struct seq_file *s, 651 unsigned long config) 652{ 653 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config); 654 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config); 655 const char *pname = "unknown"; 656 int i; 657 658 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 659 if (cfg_params[i].param == param) { 660 pname = cfg_params[i].property; 661 break; 662 } 663 } 664 665 seq_printf(s, "%s=%d", strip_prefix(pname), arg); 666} 667#endif 668 669static const struct pinconf_ops tegra_pinconf_ops = { 670 .pin_config_get = tegra_pinconf_get, 671 .pin_config_set = tegra_pinconf_set, 672 .pin_config_group_get = tegra_pinconf_group_get, 673 .pin_config_group_set = tegra_pinconf_group_set, 674#ifdef CONFIG_DEBUG_FS 675 .pin_config_dbg_show = tegra_pinconf_dbg_show, 676 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, 677 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show, 678#endif 679}; 680 681static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) 682{ 683 int i = 0; 684 const struct tegra_pingroup *g; 685 u32 val; 686 687 for (i = 0; i < pmx->soc->ngroups; ++i) { 688 g = &pmx->soc->groups[i]; 689 if (g->parked_bitmask > 0) { 690 unsigned int bank, reg; 691 692 if (g->mux_reg != -1) { 693 bank = g->mux_bank; 694 reg = g->mux_reg; 695 } else { 696 bank = g->drv_bank; 697 reg = g->drv_reg; 698 } 699 700 val = pmx_readl(pmx, bank, reg); 701 val &= ~g->parked_bitmask; 702 pmx_writel(pmx, val, bank, reg); 703 } 704 } 705} 706 707static size_t tegra_pinctrl_get_bank_size(struct device *dev, 708 unsigned int bank_id) 709{ 710 struct platform_device *pdev = to_platform_device(dev); 711 struct resource *res; 712 713 res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id); 714 715 return resource_size(res) / 4; 716} 717 718static int tegra_pinctrl_suspend(struct device *dev) 719{ 720 struct tegra_pmx *pmx = dev_get_drvdata(dev); 721 u32 *backup_regs = pmx->backup_regs; 722 u32 __iomem *regs; 723 size_t bank_size; 724 unsigned int i, k; 725 726 for (i = 0; i < pmx->nbanks; i++) { 727 bank_size = tegra_pinctrl_get_bank_size(dev, i); 728 regs = pmx->regs[i]; 729 for (k = 0; k < bank_size; k++) 730 *backup_regs++ = readl_relaxed(regs++); 731 } 732 733 return pinctrl_force_sleep(pmx->pctl); 734} 735 736static int tegra_pinctrl_resume(struct device *dev) 737{ 738 struct tegra_pmx *pmx = dev_get_drvdata(dev); 739 u32 *backup_regs = pmx->backup_regs; 740 u32 __iomem *regs; 741 size_t bank_size; 742 unsigned int i, k; 743 744 for (i = 0; i < pmx->nbanks; i++) { 745 bank_size = tegra_pinctrl_get_bank_size(dev, i); 746 regs = pmx->regs[i]; 747 for (k = 0; k < bank_size; k++) 748 writel_relaxed(*backup_regs++, regs++); 749 } 750 751 /* flush all the prior writes */ 752 readl_relaxed(pmx->regs[0]); 753 /* wait for pinctrl register read to complete */ 754 rmb(); 755 return 0; 756} 757 758DEFINE_NOIRQ_DEV_PM_OPS(tegra_pinctrl_pm, tegra_pinctrl_suspend, tegra_pinctrl_resume); 759 760static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx) 761{ 762 struct device_node *np; 763 bool has_prop = false; 764 765 np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible); 766 if (!np) 767 return has_prop; 768 769 has_prop = of_find_property(np, "gpio-ranges", NULL); 770 771 of_node_put(np); 772 773 return has_prop; 774} 775 776int tegra_pinctrl_probe(struct platform_device *pdev, 777 const struct tegra_pinctrl_soc_data *soc_data) 778{ 779 struct tegra_pmx *pmx; 780 struct resource *res; 781 int i; 782 const char **group_pins; 783 int fn, gn, gfn; 784 unsigned long backup_regs_size = 0; 785 786 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 787 if (!pmx) 788 return -ENOMEM; 789 790 pmx->dev = &pdev->dev; 791 pmx->soc = soc_data; 792 793 /* 794 * Each mux group will appear in 4 functions' list of groups. 795 * This over-allocates slightly, since not all groups are mux groups. 796 */ 797 pmx->group_pins = devm_kcalloc(&pdev->dev, pmx->soc->ngroups * 4, 798 sizeof(*pmx->group_pins), GFP_KERNEL); 799 if (!pmx->group_pins) 800 return -ENOMEM; 801 802 pmx->functions = devm_kcalloc(&pdev->dev, pmx->soc->nfunctions, 803 sizeof(*pmx->functions), GFP_KERNEL); 804 if (!pmx->functions) 805 return -ENOMEM; 806 807 group_pins = pmx->group_pins; 808 809 for (fn = 0; fn < pmx->soc->nfunctions; fn++) { 810 struct tegra_function *func = &pmx->functions[fn]; 811 812 func->name = pmx->soc->functions[fn]; 813 func->groups = group_pins; 814 815 for (gn = 0; gn < pmx->soc->ngroups; gn++) { 816 const struct tegra_pingroup *g = &pmx->soc->groups[gn]; 817 818 if (g->mux_reg == -1) 819 continue; 820 821 for (gfn = 0; gfn < 4; gfn++) 822 if (g->funcs[gfn] == fn) 823 break; 824 if (gfn == 4) 825 continue; 826 827 BUG_ON(group_pins - pmx->group_pins >= 828 pmx->soc->ngroups * 4); 829 *group_pins++ = g->name; 830 func->ngroups++; 831 } 832 } 833 834 pmx->gpio_range.name = "Tegra GPIOs"; 835 pmx->gpio_range.id = 0; 836 pmx->gpio_range.base = 0; 837 pmx->gpio_range.npins = pmx->soc->ngpios; 838 839 pmx->desc.pctlops = &tegra_pinctrl_ops; 840 pmx->desc.pmxops = &tegra_pinmux_ops; 841 pmx->desc.confops = &tegra_pinconf_ops; 842 pmx->desc.owner = THIS_MODULE; 843 pmx->desc.name = dev_name(&pdev->dev); 844 pmx->desc.pins = pmx->soc->pins; 845 pmx->desc.npins = pmx->soc->npins; 846 847 for (i = 0; ; i++) { 848 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 849 if (!res) 850 break; 851 backup_regs_size += resource_size(res); 852 } 853 pmx->nbanks = i; 854 855 pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs), 856 GFP_KERNEL); 857 if (!pmx->regs) 858 return -ENOMEM; 859 860 pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size, 861 GFP_KERNEL); 862 if (!pmx->backup_regs) 863 return -ENOMEM; 864 865 for (i = 0; i < pmx->nbanks; i++) { 866 pmx->regs[i] = devm_platform_ioremap_resource(pdev, i); 867 if (IS_ERR(pmx->regs[i])) 868 return PTR_ERR(pmx->regs[i]); 869 } 870 871 pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx); 872 if (IS_ERR(pmx->pctl)) { 873 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 874 return PTR_ERR(pmx->pctl); 875 } 876 877 tegra_pinctrl_clear_parked_bits(pmx); 878 879 if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx)) 880 pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range); 881 882 platform_set_drvdata(pdev, pmx); 883 884 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n"); 885 886 return 0; 887} 888