Searched refs:mask (Results 451 - 475 of 6712) sorted by relevance

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/linux-master/kernel/irq/
H A Dautoprobe.c27 * and a mask of potential interrupt lines is returned.
33 unsigned long mask = 0; local
96 mask |= 1 << i;
101 return mask;
107 * @val: mask of interrupts to consider
119 unsigned int mask = 0; local
127 mask |= 1 << i;
136 return mask & val;
142 * @val: mask of potential interrupts (unused)
/linux-master/drivers/md/bcache/
H A Dfeatures.h27 #define BCH_HAS_COMPAT_FEATURE(sb, mask) \
28 ((sb)->feature_compat & (mask))
29 #define BCH_HAS_RO_COMPAT_FEATURE(sb, mask) \
30 ((sb)->feature_ro_compat & (mask))
31 #define BCH_HAS_INCOMPAT_FEATURE(sb, mask) \
32 ((sb)->feature_incompat & (mask))
/linux-master/arch/mips/jazz/
H A Dirq.c29 unsigned int mask = 1 << (d->irq - JAZZ_IRQ_START); local
33 mask |= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE);
34 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask);
40 unsigned int mask = ~(1 << (d->irq - JAZZ_IRQ_START)); local
44 mask &= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE);
45 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask);
/linux-master/drivers/clk/mmp/
H A Dclk-gate.c35 tmp &= ~gate->mask;
61 tmp &= ~gate->mask;
83 return (tmp & gate->mask) == gate->val_enable;
94 void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable,
114 gate->mask = mask;
92 mmp_clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable, unsigned int gate_flags, spinlock_t *lock) argument
/linux-master/drivers/clk/imx/
H A Dclk-gpr-mux.c22 u32 mask; member in struct:imx_clk_gpr
42 val &= priv->mask;
65 return regmap_update_bits(priv->regmap, priv->reg, priv->mask, val);
76 u8 num_parents, const u32 *mux_table, u32 mask)
104 priv->mask = mask;
74 imx_clk_gpr_mux(const char *name, const char *compatible, u32 reg, const char **parent_names, u8 num_parents, const u32 *mux_table, u32 mask) argument
/linux-master/drivers/net/wireless/mediatek/mt76/
H A Dtrace.h60 TP_PROTO(struct mt76_dev *dev, u32 val, u32 mask),
62 TP_ARGS(dev, val, mask),
67 __field(u32, mask)
73 __entry->mask = mask;
78 DEV_PR_ARG, __entry->val, __entry->mask
/linux-master/drivers/power/reset/
H A Dsyscon-reboot.c21 u32 mask; member in struct:syscon_reboot_context
33 regmap_update_bits(ctx->map, ctx->offset, ctx->mask, ctx->value);
67 mask_err = of_property_read_u32(pdev->dev.of_node, "mask", &ctx->mask);
69 dev_err(dev, "unable to read 'value' and 'mask'");
75 ctx->value = ctx->mask;
76 ctx->mask = 0xFFFFFFFF;
78 /* support value without mask*/
79 ctx->mask = 0xFFFFFFFF;
/linux-master/drivers/mfd/
H A Drt5033.c21 { .mask = RT5033_PMIC_IRQ_BUCKOCP, },
22 { .mask = RT5033_PMIC_IRQ_BUCKLV, },
23 { .mask = RT5033_PMIC_IRQ_SAFELDOLV, },
24 { .mask = RT5033_PMIC_IRQ_LDOLV, },
25 { .mask = RT5033_PMIC_IRQ_OT, },
26 { .mask = RT5033_PMIC_IRQ_VDDA_UV, },
/linux-master/drivers/gpu/drm/amd/display/dc/basics/
H A Dcustom_float.c133 uint32_t mask = 1 << i; local
135 if (mantissa & mask)
136 value |= mask;
142 uint32_t mask = 1 << j; local
144 if (exponenta & mask)
145 value |= mask << i;
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/vfn/
H A Dtu102.c29 tu102_vfn_intr_reset(struct nvkm_intr *intr, int leaf, u32 mask) argument
33 nvkm_wr32(vfn->subdev.device, vfn->addr.priv + 0x1000 + (leaf * 4), mask);
37 tu102_vfn_intr_allow(struct nvkm_intr *intr, int leaf, u32 mask) argument
41 nvkm_wr32(vfn->subdev.device, vfn->addr.priv + 0x1200 + (leaf * 4), mask);
45 tu102_vfn_intr_block(struct nvkm_intr *intr, int leaf, u32 mask) argument
49 nvkm_wr32(vfn->subdev.device, vfn->addr.priv + 0x1400 + (leaf * 4), mask);
/linux-master/net/netfilter/
H A Dnf_conntrack_broadcast.c29 __be32 mask = 0; local
48 mask = ifa->ifa_mask;
54 if (mask == 0)
67 exp->mask.src.u3.ip = mask;
68 exp->mask.src.u.udp.port = htons(0xFFFF);
/linux-master/arch/mips/bcm63xx/
H A Dclk.c43 static void bcm_hwclock_set(u32 mask, int enable) argument
49 reg |= mask;
51 reg &= ~mask;
60 u32 mask; local
63 mask = CKCTL_6338_ENET_EN;
65 mask = CKCTL_6345_ENET_EN;
67 mask = CKCTL_6348_ENET_EN;
70 mask = CKCTL_6358_EMUSB_EN;
71 bcm_hwclock_set(mask, enable);
90 u32 mask; local
245 u32 mask; local
270 u32 mask; local
[all...]
/linux-master/arch/x86/kernel/apic/
H A Dx2apic_phys.c54 __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest) argument
66 for_each_cpu(query_cpu, mask) {
75 static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) argument
77 __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
81 x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) argument
83 __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
/linux-master/arch/powerpc/kernel/
H A Dsmp.c373 void arch_send_call_function_ipi_mask(const struct cpumask *mask) argument
377 for_each_cpu(cpu, mask)
570 void tick_broadcast(const struct cpumask *mask) argument
574 for_each_cpu(cpu, mask)
608 * cpus to clear pending mask, etc.
738 struct cpumask *mask; local
741 mask = srcmask(j);
743 cpumask_or(dstmask(k), dstmask(k), mask); local
748 mask = srcmask(i);
750 cpumask_or(dstmask(k), dstmask(k), mask); local
920 update_mask_from_threadgroup(cpumask_var_t *mask, struct thread_groups *tg, int cpu, int cpu_group_start) argument
948 cpumask_var_t *mask = NULL; local
1410 update_mask_by_l2(int cpu, cpumask_var_t *mask) argument
1523 update_coregroup_mask(int cpu, cpumask_var_t *mask) argument
1563 cpumask_var_t mask; local
1663 struct cpumask *mask = cpu_l2_cache_mask(cpu); local
[all...]
/linux-master/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c369 static inline void comphy_reg_set(void __iomem *addr, u32 data, u32 mask) argument
374 val = (val & ~mask) | (data & mask);
378 static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask) argument
383 val = (val & ~mask) | (data & mask);
389 u32 offset, u16 data, u16 mask)
394 data, mask);
398 u16 reg, u16 data, u16 mask)
404 data, mask);
388 comphy_set_indirect(struct mvebu_a3700_comphy_priv *priv, u32 offset, u16 data, u16 mask) argument
397 comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane, u16 reg, u16 data, u16 mask) argument
447 comphy_periph_reg_set(struct mvebu_a3700_comphy_lane *lane, u8 reg, u32 data, u32 mask) argument
534 u32 mask, data, ref_clk; local
631 u32 mask, data, speed_sel; local
823 u32 mask, data, cfg, ref_clk; local
988 u32 mask, data, ref_clk; local
1088 u32 mask, data; local
[all...]
/linux-master/drivers/irqchip/
H A Dirq-hip04.c93 u32 mask = 1 << (hip04_irq(d) % 32); local
96 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR +
103 u32 mask = 1 << (hip04_irq(d) % 32); local
106 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET +
152 u32 val, mask, bit; local
164 mask = 0xffff << shift;
166 val = readl_relaxed(reg) & ~mask;
175 static void hip04_ipi_send_mask(struct irq_data *d, const struct cpumask *mask) argument
182 /* Convert our logical CPU mask into a physical one. */
183 for_each_cpu(cpu, mask)
231 u32 mask, i; local
[all...]
H A Dirq-ingenic-tcu.c53 u32 mask = d->mask; local
56 regmap_write(map, ct->regs.ack, mask);
57 regmap_write(map, ct->regs.enable, mask);
58 *ct->mask_cache |= mask;
67 u32 mask = d->mask; local
70 regmap_write(map, ct->regs.disable, mask);
71 *ct->mask_cache &= ~mask;
80 u32 mask local
[all...]
/linux-master/tools/testing/radix-tree/
H A Dmultiorder.c60 unsigned long mask = (1UL << order[i]) - 1; local
62 assert((xas.xa_index | mask) == (index[i] | mask));
65 assert((item->index | mask) == (index[i] | mask));
109 unsigned long mask; local
112 mask = (1UL << order[k]) - 1;
114 assert((xas.xa_index | mask) == (tag_index[i] | mask));
116 assert((item->index | mask)
126 int mask, k; local
[all...]
/linux-master/drivers/ssb/
H A Ddriver_extif.c31 u32 mask, u32 value)
33 value &= mask;
34 value |= extif_read32(extif, offset) & ~mask;
148 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask) argument
150 return extif_read32(extif, SSB_EXTIF_GPIO_IN) & mask;
153 u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value) argument
160 mask, value);
166 u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value) argument
173 mask, value);
179 u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u3 argument
30 extif_write32_masked(struct ssb_extif *extif, u16 offset, u32 mask, u32 value) argument
191 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value) argument
[all...]
/linux-master/drivers/net/ethernet/netronome/nfp/abm/
H A Dcls.c15 u8 mask; member in struct:nfp_abm_u32_match
49 if (knode->val || knode->mask) {
81 NL_SET_ERR_MSG_MOD(extack, "offset mask - variable offsetting not supported");
88 if (k->val & ~k->mask) {
89 NL_SET_ERR_MSG_MOD(extack, "mask does not cover the key");
92 if (be32_to_cpu(k->mask) >> tos_off & ~abm->dscp_mask) {
95 "u32 offload: requested mask %x FW can support only %x\n",
96 be32_to_cpu(k->mask) >> tos_off, abm->dscp_mask);
113 if ((prio & iter->mask) == iter->val)
131 /* FW mask applie
176 u8 mask, val; local
[all...]
/linux-master/drivers/soundwire/
H A Dsysfs_slave_dpn.c60 unsigned long mask; \
66 mask = slave->prop.source_ports; \
69 mask = slave->prop.sink_ports; \
73 for_each_set_bit(bit, &mask, 32) { \
120 unsigned long mask; \
128 mask = slave->prop.source_ports; \
131 mask = slave->prop.sink_ports; \
135 for_each_set_bit(bit, &mask, 32) { \
282 unsigned long mask; local
286 mask
[all...]
/linux-master/fs/nfsd/
H A Dnfs3acl.c43 if (argp->mask & ~NFS_ACL_MASK) {
47 resp->mask = argp->mask;
49 if (resp->mask & (NFS_ACL|NFS_ACLCNT)) {
61 if (resp->mask & (NFS_DFACL|NFS_DFACLCNT)) {
137 if (xdr_stream_decode_u32(xdr, &args->mask) < 0)
150 if (xdr_stream_decode_u32(xdr, &argp->mask) < 0)
152 if (argp->mask & ~NFS_ACL_MASK)
154 if (!nfs_stream_decode_acl(xdr, NULL, (argp->mask & NFS_ACL) ?
157 if (!nfs_stream_decode_acl(xdr, NULL, (argp->mask
[all...]
/linux-master/drivers/firmware/imx/
H A Dimx-scu-irq.c40 u32 mask; member in struct:imx_sc_msg_irq_enable
47 u32 mask; member in struct:scu_wakeup
91 if (scu_irq_wakeup[i].mask) {
105 if (scu_irq_wakeup[i].mask & irq_status) {
107 scu_irq_wakeup[i].wakeup_src = irq_status & scu_irq_wakeup[i].mask;
142 int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable) argument
158 msg.mask = mask;
163 pr_err("enable irq failed, group %d, mask %d, ret %d\n",
164 group, mask, re
[all...]
/linux-master/drivers/net/dsa/mv88e6xxx/
H A Dglobal2_scratch.c56 u8 mask = (1 << (offset & 0x7)); local
64 *set = !!(mask & val);
83 u8 mask = (1 << (offset & 0x7)); local
92 val |= mask;
94 val &= ~mask;
130 u8 mask = (1 << (pin & 0x7)); local
137 chip->gpio_data[offset] |= mask;
139 chip->gpio_data[offset] &= ~mask;
196 u8 mask = (0x7 << offset); local
204 *func = (val & mask) >> offse
220 u8 mask = (0x7 << offset); local
[all...]
/linux-master/arch/arm/mach-omap2/
H A Dprm33xx.c32 static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) argument
37 v &= ~mask;
85 u32 mask = 1 << shift; local
87 am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
116 u32 mask = 1 << st_shift; local
123 am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
126 mask = 1 << shift;
128 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
328 u32 mask local
[all...]

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