Searched refs:val (Results 276 - 300 of 10961) sorted by relevance

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/linux-master/include/linux/
H A D	iversion.h	102 * @val: new i_version value to set 104 * Set @inode's i_version field to @val. This function is for use by 111 inode_set_iversion_raw(struct inode *inode, u64 val) argument 113 atomic64_set(&inode->i_version, val); 136 * @val: new i_version to set 142 inode_set_max_iversion_raw(struct inode *inode, u64 val) argument 147 if (cur > val) 149 } while (!atomic64_try_cmpxchg(&inode->i_version, &cur, val)); 155 * @val: new i_version value to set 157 * Set @inode's i_version field to @val 165 inode_set_iversion(struct inode *inode, u64 val) argument 187 inode_set_iversion_queried(struct inode *inode, u64 val) argument [all...]
/linux-master/drivers/phy/ti/
H A D	phy-omap-control.c	26 u32 val; local 45 val = readl(control_phy->pcie_pcs); 46 val &= ~(OMAP_CTRL_PCIE_PCS_MASK << 48 val |= (delay << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT); 49 writel(val, control_phy->pcie_pcs); 60 u32 val; local 78 val = readl(control_phy->power); 83 val &= ~OMAP_CTRL_DEV_PHY_PD; 85 val |= OMAP_CTRL_DEV_PHY_PD; 94 val 146 u32 val; local 164 u32 val; local 183 u32 val; local [all...]
/linux-master/drivers/net/dsa/mv88e6xxx/
H A D	global2_scratch.c	57 u8 val; local 60 err = mv88e6xxx_g2_scratch_read(chip, reg, &val); 64 *set = !!(mask & val); 84 u8 val; local 87 err = mv88e6xxx_g2_scratch_read(chip, reg, &val); 92 val |= mask; 94 val &= ~mask; 96 return mv88e6xxx_g2_scratch_write(chip, reg, val); 109 int val = 0; local 114 pin, &val); 154 int val = 0; local 198 u8 val; local 222 u8 val; local 260 u8 val; local 310 u8 val; local [all...]
/linux-master/include/video/
H A D	vga.h	209 static inline void vga_io_w (unsigned short port, unsigned char val) argument 211 outb_p(val, port); 215 unsigned char val) 217 outw(VGA_OUT16VAL (val, reg), port); 225 static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val) argument 227 writeb (val, regbase + port); 231 unsigned char reg, unsigned char val) 233 writew (VGA_OUT16VAL (val, reg), regbase + port); 244 static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val) argument 247 vga_mm_w (regbase, port, val); 214 vga_io_w_fast(unsigned short port, unsigned char reg, unsigned char val) argument 230 vga_mm_w_fast(void __iomem *regbase, unsigned short port, unsigned char reg, unsigned char val) argument 253 vga_w_fast(void __iomem *regbase, unsigned short port, unsigned char reg, unsigned char val) argument 273 vga_wcrt(void __iomem *regbase, unsigned char reg, unsigned char val) argument 289 vga_io_wcrt(unsigned char reg, unsigned char val) argument 305 vga_mm_wcrt(void __iomem *regbase, unsigned char reg, unsigned char val) argument 326 vga_wseq(void __iomem *regbase, unsigned char reg, unsigned char val) argument 342 vga_io_wseq(unsigned char reg, unsigned char val) argument 358 vga_mm_wseq(void __iomem *regbase, unsigned char reg, unsigned char val) argument 378 vga_wgfx(void __iomem *regbase, unsigned char reg, unsigned char val) argument 394 vga_io_wgfx(unsigned char reg, unsigned char val) argument 410 vga_mm_wgfx(void __iomem *regbase, unsigned char reg, unsigned char val) argument 431 vga_wattr(void __iomem *regbase, unsigned char reg, unsigned char val) argument 443 vga_io_wattr(unsigned char reg, unsigned char val) argument 455 vga_mm_wattr(void __iomem *regbase, unsigned char reg, unsigned char val) argument [all...]
/linux-master/drivers/gpu/drm/msm/adreno/
H A D	adreno_common.xml.h	209 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) argument 211 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; 215 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) argument 217 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; 221 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) argument 223 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; 232 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) argument 234 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; 238 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) argument 240 assert(!(val 257 AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) argument 263 AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) argument 269 AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) argument 277 AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) argument 283 AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) argument 291 AXXX_CP_CSQ_AVAIL_RING(uint32_t val) argument 297 AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) argument 303 AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) argument 311 AXXX_CP_STQ_AVAIL_ST(uint32_t val) argument 319 AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) argument 327 AXXX_SCRATCH_UMSK_UMSK(uint32_t val) argument 333 AXXX_SCRATCH_UMSK_SWAP(uint32_t val) argument 386 AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) argument 392 AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) argument 400 AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) argument 406 AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) argument 414 AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) argument 420 AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) argument [all...]
/linux-master/drivers/scsi/
H A D	nsp32_io.h	14 unsigned char val) 16 outb(val, (base + index)); 27 unsigned short val) 29 outw(val, (base + index)); 40 unsigned long val) 42 outl(val, (base + index)); 55 unsigned char val) 61 writeb(val, ptr); 76 unsigned short val) 82 writew(cpu_to_le16(val), pt 12 nsp32_write1(unsigned int base, unsigned int index, unsigned char val) argument 25 nsp32_write2(unsigned int base, unsigned int index, unsigned short val) argument 38 nsp32_write4(unsigned int base, unsigned int index, unsigned long val) argument 53 nsp32_mmio_write1(unsigned long base, unsigned int index, unsigned char val) argument 74 nsp32_mmio_write2(unsigned long base, unsigned int index, unsigned short val) argument 95 nsp32_mmio_write4(unsigned long base, unsigned int index, unsigned long val) argument 125 nsp32_index_write1(unsigned int base, unsigned int reg, unsigned char val) argument 140 nsp32_index_write2(unsigned int base, unsigned int reg, unsigned short val) argument 160 nsp32_index_write4(unsigned int base, unsigned int reg, unsigned long val) argument 188 nsp32_mmio_index_write1(unsigned long base, unsigned int reg, unsigned char val) argument 213 nsp32_mmio_index_write2(unsigned long base, unsigned int reg, unsigned short val) argument [all...]
/linux-master/drivers/base/regmap/
H A D	regmap-fsi.c	15 static int regmap_fsi32_reg_read(void *context, unsigned int reg, unsigned int *val) argument 24 *val = v; 28 static int regmap_fsi32_reg_write(void *context, unsigned int reg, unsigned int val) argument 30 u32 v = val; 40 static int regmap_fsi32le_reg_read(void *context, unsigned int reg, unsigned int *val) argument 49 *val = be32_to_cpu(v); 53 static int regmap_fsi32le_reg_write(void *context, unsigned int reg, unsigned int val) argument 55 __be32 v = cpu_to_be32(val); 65 static int regmap_fsi16_reg_read(void *context, unsigned int reg, unsigned int *val) argument 74 *val 78 regmap_fsi16_reg_write(void *context, unsigned int reg, unsigned int val) argument 94 regmap_fsi16le_reg_read(void *context, unsigned int reg, unsigned int *val) argument 107 regmap_fsi16le_reg_write(void *context, unsigned int reg, unsigned int val) argument 123 regmap_fsi8_reg_read(void *context, unsigned int reg, unsigned int *val) argument 136 regmap_fsi8_reg_write(void *context, unsigned int reg, unsigned int val) argument [all...]
/linux-master/drivers/gpu/drm/i915/soc/
H A D	intel_dram.c	142 u32 val; local 145 val = vlv_cck_read(i915, CCK_FUSE_REG); 148 switch ((val >> 2) & 0x7) { 160 u32 val; local 163 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 166 switch ((val >> 6) & 3) { 201 static int skl_get_dimm_size(u16 val) argument 203 return (val & SKL_DRAM_SIZE_MASK) * 8; 206 static int skl_get_dimm_width(u16 val) argument 208 if (skl_get_dimm_size(val) 223 skl_get_dimm_ranks(u16 val) argument 234 icl_get_dimm_size(u16 val) argument 239 icl_get_dimm_width(u16 val) argument 256 icl_get_dimm_ranks(u16 val) argument 274 skl_dram_get_dimm_info(struct drm_i915_private *i915, struct dram_dimm_info *dimm, int channel, char dimm_name, u16 val) argument 295 skl_dram_get_channel_info(struct drm_i915_private *i915, struct dram_channel_info *ch, int channel, u32 val) argument 339 u32 val; local 377 u32 val; local 415 bxt_get_dimm_size(u32 val) argument 434 bxt_get_dimm_width(u32 val) argument 444 bxt_get_dimm_ranks(u32 val) argument 460 bxt_get_dimm_type(u32 val) argument 480 bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val) argument 495 u32 val; local 543 u32 val = 0; local 621 u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL); local [all...]
/linux-master/mm/
H A D	ptdump.c	33 pgd_t val = READ_ONCE(*pgd); local 37 if (pgd_page(val) == virt_to_page(lm_alias(kasan_early_shadow_p4d))) 42 st->effective_prot(st, 0, pgd_val(val)); 44 if (pgd_leaf(val)) { 45 st->note_page(st, addr, 0, pgd_val(val)); 56 p4d_t val = READ_ONCE(*p4d); local 60 if (p4d_page(val) == virt_to_page(lm_alias(kasan_early_shadow_pud))) 65 st->effective_prot(st, 1, p4d_val(val)); 67 if (p4d_leaf(val)) { 68 st->note_page(st, addr, 1, p4d_val(val)); 79 pud_t val = READ_ONCE(*pud); local 102 pmd_t val = READ_ONCE(*pmd); local 123 pte_t val = ptep_get_lockless(pte); local [all...]
/linux-master/drivers/net/wireless/realtek/rtw89/
H A D	fw.h	399 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) argument 401 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); 404 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) argument 406 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 409 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) argument 411 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); 414 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) argument 416 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); 419 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) argument 421 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BI 424 RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) argument 429 RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) argument 434 RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) argument 439 RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) argument 444 RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) argument 449 RTW89_SET_EDCA_SEL(void *cmd, u32 val) argument 454 RTW89_SET_EDCA_BAND(void *cmd, u32 val) argument 459 RTW89_SET_EDCA_WMM(void *cmd, u32 val) argument 464 RTW89_SET_EDCA_AC(void *cmd, u32 val) argument 469 RTW89_SET_EDCA_PARAM(void *cmd, u32 val) argument 622 SET_CTRL_INFO_MACID(void *table, u32 val) argument 627 SET_CTRL_INFO_OPERATION(void *table, u32 val) argument 632 SET_CMC_TBL_DATARATE(void *table, u32 val) argument 639 SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) argument 646 SET_CMC_TBL_DATA_BW(void *table, u32 val) argument 653 SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) argument 660 SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) argument 667 SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) argument 674 SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) argument 681 SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) argument 688 SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) argument 695 SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) argument 702 SET_CMC_TBL_DISRTSFB(void *table, u32 val) argument 709 SET_CMC_TBL_DISDATAFB(void *table, u32 val) argument 716 SET_CMC_TBL_TRYRATE(void *table, u32 val) argument 723 SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) argument 730 SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) argument 737 SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) argument 744 SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) argument 751 SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) argument 758 SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) argument 765 SET_CMC_TBL_RTSRATE(void *table, u32 val) argument 772 SET_CMC_TBL_VCS_STBC(void *table, u32 val) argument 779 SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) argument 786 SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) argument 793 SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) argument 800 SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) argument 807 SET_CMC_TBL_RTS_EN(void *table, u32 val) argument 814 SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) argument 821 SET_CMC_TBL_CCA_RTS(void *table, u32 val) argument 828 SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) argument 835 SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) argument 842 SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) argument 849 SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) argument 856 SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) argument 863 SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) argument 870 SET_CMC_TBL_BA_BMAP(void *table, u32 val) argument 877 SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) argument 884 SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) argument 891 SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) argument 898 SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) argument 905 SET_CMC_TBL_SECTYPE(void *table, u32 val) argument 912 SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) argument 919 SET_CMC_TBL_BMC(void *table, u32 val) argument 926 SET_CMC_TBL_MBSSID(void *table, u32 val) argument 933 SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) argument 940 SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) argument 947 SET_CMC_TBL_DATA_DCM(void *table, u32 val) argument 954 SET_CMC_TBL_DATA_ER(void *table, u32 val) argument 961 SET_CMC_TBL_DATA_LDPC(void *table, u32 val) argument 968 SET_CMC_TBL_DATA_STBC(void *table, u32 val) argument 975 SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) argument 982 SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) argument 989 SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) argument 996 SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) argument 1003 SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) argument 1010 SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) argument 1017 SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) argument 1024 SET_CMC_TBL_CTRL_CNT(void *table, u32 val) argument 1031 SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) argument 1038 SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) argument 1045 SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) argument 1052 SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) argument 1059 SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) argument 1066 SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) argument 1073 SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) argument 1080 SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) argument 1087 SET_CMC_TBL_ANTSEL_A(void *table, u32 val) argument 1094 SET_CMC_TBL_ANTSEL_B(void *table, u32 val) argument 1101 SET_CMC_TBL_ANTSEL_C(void *table, u32 val) argument 1108 SET_CMC_TBL_ANTSEL_D(void *table, u32 val) argument 1116 SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val) argument 1123 SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val) argument 1130 SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val) argument 1137 SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val) argument 1145 SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) argument 1152 SET_CMC_TBL_PAID(void *table, u32 val) argument 1159 SET_CMC_TBL_ULDL(void *table, u32 val) argument 1166 SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) argument 1172 SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) argument 1179 SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) argument 1186 SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) argument 1193 SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) argument 1200 SET_CMC_TBL_NC(void *table, u32 val) argument 1207 SET_CMC_TBL_NR(void *table, u32 val) argument 1214 SET_CMC_TBL_NG(void *table, u32 val) argument 1221 SET_CMC_TBL_CB(void *table, u32 val) argument 1228 SET_CMC_TBL_CS(void *table, u32 val) argument 1235 SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) argument 1242 SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) argument 1249 SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) argument 1256 SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) argument 1263 SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) argument 1270 SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) argument 1277 SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val) argument 1285 SET_CMC_TBL_CSI_BW(void *table, u32 val) argument 1435 SET_DCTL_MACID_V1(void *table, u32 val) argument 1440 SET_DCTL_OPERATION_V1(void *table, u32 val) argument 1446 SET_DCTL_QOS_FIELD_V1(void *table, u32 val) argument 1454 SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val) argument 1462 SET_DCTL_QOS_DATA_V1(void *table, u32 val) argument 1470 SET_DCTL_AES_IV_L_V1(void *table, u32 val) argument 1478 SET_DCTL_AES_IV_H_V1(void *table, u32 val) argument 1486 SET_DCTL_SEQ0_V1(void *table, u32 val) argument 1494 SET_DCTL_SEQ1_V1(void *table, u32 val) argument 1502 SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val) argument 1510 SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val) argument 1518 SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val) argument 1526 SET_DCTL_WITH_LLC_V1(void *table, u32 val) argument 1534 SET_DCTL_SEQ2_V1(void *table, u32 val) argument 1542 SET_DCTL_SEQ3_V1(void *table, u32 val) argument 1550 SET_DCTL_TGT_IND_V1(void *table, u32 val) argument 1558 SET_DCTL_TGT_IND_EN_V1(void *table, u32 val) argument 1566 SET_DCTL_HTC_LB_V1(void *table, u32 val) argument 1574 SET_DCTL_MHDR_LEN_V1(void *table, u32 val) argument 1582 SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val) argument 1590 SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val) argument 1598 SET_DCTL_HTC_ORDER_V1(void *table, u32 val) argument 1606 SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val) argument 1614 SET_DCTL_WAPI_V1(void *table, u32 val) argument 1622 SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val) argument 1630 SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val) argument 1637 SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val) argument 1644 SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val) argument 1651 SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val) argument 1658 SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val) argument 1665 SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val) argument 1672 SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val) argument 1680 SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val) argument 1688 SET_DCTL_SEC_ENT0_V1(void *table, u32 val) argument 1695 SET_DCTL_SEC_ENT1_V1(void *table, u32 val) argument 1702 SET_DCTL_SEC_ENT2_V1(void *table, u32 val) argument 1709 SET_DCTL_SEC_ENT3_V1(void *table, u32 val) argument 1716 SET_DCTL_SEC_ENT4_V1(void *table, u32 val) argument 1723 SET_DCTL_SEC_ENT5_V1(void *table, u32 val) argument 1730 SET_DCTL_SEC_ENT6_V1(void *table, u32 val) argument 1830 SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val) argument 1835 SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val) argument 1840 SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val) argument 1845 SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val) argument 1897 SET_GENERAL_PKT_MACID(void *h2c, u32 val) argument 1902 SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) argument 1907 SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) argument 1912 SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) argument 1917 SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) argument 1922 SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) argument 1927 SET_LOG_CFG_LEVEL(void *h2c, u32 val) argument 1932 SET_LOG_CFG_PATH(void *h2c, u32 val) argument 1937 SET_LOG_CFG_COMP(void *h2c, u32 val) argument 1942 SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) argument 1989 SET_LPS_PARM_MACID(void *h2c, u32 val) argument 1994 SET_LPS_PARM_PSMODE(void *h2c, u32 val) argument 1999 SET_LPS_PARM_RLBM(void *h2c, u32 val) argument 2004 SET_LPS_PARM_SMARTPS(void *h2c, u32 val) argument 2009 SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) argument 2014 SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) argument 2019 SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) argument 2024 SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) argument 2029 SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) argument 2034 SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) argument 2050 RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val) argument 2055 RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val) argument 2060 RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val) argument 2065 RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val) argument 2070 RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val) argument 2075 RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val) argument 2080 RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val) argument 2085 RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val) argument 2090 RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val) argument 2095 RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val) argument 2100 RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val) argument 2105 RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val) argument 2110 RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val) argument 2115 RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val) argument 2120 RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val) argument 2125 RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val) argument 2130 RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val) argument 2135 RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val) argument 2140 RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val) argument 2145 RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val) argument 2150 RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val) argument 2155 RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val) argument 2160 RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val) argument 2165 RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val) argument 2170 RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val) argument 2175 RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val) argument 2180 RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val) argument 2185 RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val) argument 2190 RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val) argument 2195 RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val) argument 2200 RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val) argument 2205 RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val) argument 2210 RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val) argument 2215 RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val) argument 2220 RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val) argument 2225 RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val) argument 2230 RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val) argument 2235 RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val) argument 2240 RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val) argument 2245 RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val) argument 2250 RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val) argument 2255 RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val) argument 2260 RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val) argument 2265 RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val) argument 2270 RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val) argument 2275 RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val) argument 2280 RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val) argument 2285 RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val) argument 2290 RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val) argument 2295 RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val) argument 2300 RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val) argument 2305 RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val) argument 2369 RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) argument 2374 RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) argument 2435 RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) argument 2440 RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) argument 2445 RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) argument 2450 RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) argument 2455 RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) argument 2460 RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) argument 2465 RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) argument 2470 RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) argument 2475 RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) argument 2480 RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) argument 2485 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) argument 2490 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) argument 2495 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) argument 2500 RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) argument 2505 RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset) argument 2510 RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset) argument 2515 RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset) argument 2520 RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset) argument 2525 RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset) argument 2530 RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset) argument 2535 RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset) argument 2540 RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset) argument 2545 RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset) argument 2550 RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset) argument 2555 RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset) argument 2560 RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset) argument 2565 RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset) argument 2570 RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset) argument 2575 RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset) argument 2580 RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset) argument 2585 RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset) argument 2590 RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset) argument 2595 RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset) argument 2600 RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset) argument 2605 RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset) argument 2610 RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset) argument 2615 RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset) argument 2620 RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset) argument 2625 RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset) argument 2630 RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset) argument 2635 RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset) argument 2640 RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset) argument 2645 RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset) argument 2650 RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset) argument 2655 RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) argument 2660 RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) argument 2665 RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) argument 2670 RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) argument 2675 RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val) argument 2680 RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val) argument 2685 RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val) argument 2690 RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val) argument 2695 RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val) argument 2700 RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val) argument 2705 RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val) argument 2710 RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val) argument 2715 RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val) argument 2720 RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val) argument 2725 RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val) argument 2730 RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val) argument 2735 RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val) argument 2740 RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val) argument 2745 RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val) argument 2750 RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val) argument 2755 RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val) argument 2760 RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) argument 2765 RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) argument 2770 RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) argument 2775 RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) argument 2780 RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) argument 2785 RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val) argument 2790 RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val) argument 2795 RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val) argument 2986 RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val) argument 2991 RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val) argument 2996 RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val) argument 3001 RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val) argument 3006 RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val) argument 3011 RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val) argument 3016 RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val) argument 3021 RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val) argument 3026 RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val) argument 3031 RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val) argument 3036 RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val) argument 3046 RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val) argument 3051 RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val) argument 3056 RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val) argument 3061 RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val) argument 3097 RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val) argument 3102 RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val) argument 3107 RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val) argument 3112 RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val) argument 3117 RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val) argument 3122 RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val) argument 3127 RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val) argument 3132 RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val) argument 3137 RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val) argument 3142 RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val) argument 3147 RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val) argument 3152 RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val) argument 3157 RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val) argument 3162 RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val) argument 3167 RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val) argument 3172 RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val) argument 3177 RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val) argument 3182 RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val) argument 3187 RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val) argument 3192 RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val) argument 3217 RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val) argument 3222 RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val) argument 3227 RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val) argument 3232 RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val) argument 3237 RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val) argument 3242 RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val) argument 3247 RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val) argument 3252 RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val) argument 3257 RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val) argument 3262 RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val) argument 3267 RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val) argument 3272 RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val) argument 3277 RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val) argument 3282 RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val) argument 3287 RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val) argument 3300 RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val) argument 3305 RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val) argument 3310 RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val) argument 3315 RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val) argument 3320 RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val) argument 3325 RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val) argument 3336 RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val) argument 3341 RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val) argument 3346 RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val) argument 3351 RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val) argument 3369 RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val) argument 3375 RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val) argument 3381 RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val) argument 3386 RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val) argument 3391 RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val) argument 3397 RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val) argument 3403 RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val) argument 3409 RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val) argument 3415 RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val) argument [all...]
/linux-master/drivers/media/i2c/s5c73m3/
H A D	s5c73m3-ctrls.c	39 ctrl->val = V4L2_AUTO_FOCUS_STATUS_BUSY; 43 ctrl->val = V4L2_AUTO_FOCUS_STATUS_REACHED; 51 ctrl->val = V4L2_AUTO_FOCUS_STATUS_FAILED; 78 static int s5c73m3_set_colorfx(struct s5c73m3 *state, int val) argument 90 if (colorfx[i][0] != val) 113 switch (ctrls->exposure_metering->val) { 129 u16 exp_bias = ctrls->exposure_bias->val; 135 ctrls->exposure_bias->val, ctrls->exposure_metering->val, ret); 140 static int s5c73m3_set_white_balance(struct s5c73m3 *state, int val) argument 234 s5c73m3_set_contrast(struct s5c73m3 *state, int val) argument 240 s5c73m3_set_saturation(struct s5c73m3 *state, int val) argument 246 s5c73m3_set_sharpness(struct s5c73m3 *state, int val) argument 252 s5c73m3_set_iso(struct s5c73m3 *state, int val) argument 264 s5c73m3_set_stabilization(struct s5c73m3 *state, int val) argument 288 s5c73m3_set_scene_program(struct s5c73m3 *state, int val) argument 313 s5c73m3_set_power_line_freq(struct s5c73m3 *state, int val) argument [all...]
/linux-master/arch/sparc/kernel/
H A D	pcr.c	57 u64 val; local 60 __asm__ __volatile__("rd %%pcr, %0" : "=r" (val)); 61 return val; 64 static void direct_pcr_write(unsigned long reg_num, u64 val) argument 67 __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (val)); 72 u64 val; local 75 __asm__ __volatile__("rd %%pic, %0" : "=r" (val)); 76 return val; 79 static void direct_pic_write(unsigned long reg_num, u64 val) argument 91 "rd %%pic, %%g0" : : "r" (val)); 111 n2_pcr_write(unsigned long reg_num, u64 val) argument 146 unsigned long val; local 153 n4_pcr_write(unsigned long reg_num, u64 val) argument 160 unsigned long val; local 169 n4_pic_write(unsigned long reg_num, u64 val) argument 197 unsigned long val; local 204 n5_pcr_write(unsigned long reg_num, u64 val) argument 223 unsigned long val; local 230 m7_pcr_write(unsigned long reg_num, u64 val) argument [all...]
/linux-master/drivers/media/pci/bt8xx/
H A D	bttv-audio-hook.c	88 unsigned int val, con; local 93 val = gpio_read(); 106 if (con != (val & 0x300)) { 112 switch (val & 0x70) { 159 int val; local 174 val = 0x02; 177 val = 0x01; 182 gpio_bits(0x03, val); 190 int val = 0; local 205 val 223 int val = 0; local 294 unsigned long val; local 330 unsigned int val = 0; local 371 unsigned int val; local 410 unsigned long val; local [all...]
/linux-master/drivers/media/platform/qcom/camss/
H A D	camss-csid-4-7.c	202 u32 val; local 223 val = ((CAMSS_CSID_TG_VC_CFG_V_BLANKING & 0xff) << 24) | 225 writel_relaxed(val, csid->base + CAMSS_CSID_TG_VC_CFG); 228 val = ((num_bytes_per_line & 0x1fff) << 16) | 230 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_0(0)); 233 val = format->data_type; 234 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_1(0)); 237 val = tg->mode - 1; 238 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_2(0)); 246 val 294 csid_configure_testgen_pattern(struct csid_device *csid, s32 val) argument [all...]
/linux-master/drivers/video/fbdev/
H A D	gbefb.c	201 unsigned int val, y, vpixen_off; local 206 val = gbe->vt_xy; 207 if (GET_GBE_FIELD(VT_XY, FREEZE, val) == 1) 211 val = gbe->ovr_control; 212 SET_GBE_FIELD(OVR_CONTROL, OVR_DMA_ENABLE, val, 0); 213 gbe->ovr_control = val; 215 val = gbe->frm_control; 216 SET_GBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, val, 0); 217 gbe->frm_control = val; 219 val 310 unsigned int val, i; local 533 unsigned int val; local 642 unsigned int val; local [all...]
/linux-master/drivers/scsi/aic94xx/
H A D	aic94xx_reg.c	15 * this function is *offs = val. 18 unsigned long offs, u8 val) 21 outb(val, 24 writeb(val, asd_ha->io_handle[0].addr + offs); 29 unsigned long offs, u16 val) 32 outw(val, 35 writew(val, asd_ha->io_handle[0].addr + offs); 40 unsigned long offs, u32 val) 43 outl(val, 46 writel(val, asd_h 17 asd_write_byte(struct asd_ha_struct *asd_ha, unsigned long offs, u8 val) argument 28 asd_write_word(struct asd_ha_struct *asd_ha, unsigned long offs, u16 val) argument 39 asd_write_dword(struct asd_ha_struct *asd_ha, unsigned long offs, u32 val) argument 54 u8 val; local 67 u16 val; local 80 u32 val; local 177 __asd_write_reg_byte(struct asd_ha_struct *asd_ha, u32 reg, u8 val) argument 228 u8 val; local [all...]
/linux-master/drivers/net/ethernet/huawei/hinic/
H A D	hinic_hw_api_cmd.h	19 #define HINIC_API_CMD_PI_SET(val, member) \ 20 (((u32)(val) & HINIC_API_CMD_PI_##member##_MASK) << \ 23 #define HINIC_API_CMD_PI_CLEAR(val, member) \ 24 ((val) & (~(HINIC_API_CMD_PI_##member##_MASK \ 31 #define HINIC_API_CMD_CHAIN_REQ_SET(val, member) \ 32 (((u32)(val) & HINIC_API_CMD_CHAIN_REQ_##member##_MASK) << \ 35 #define HINIC_API_CMD_CHAIN_REQ_GET(val, member) \ 36 (((val) >> HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT) & \ 39 #define HINIC_API_CMD_CHAIN_REQ_CLEAR(val, member) \ 40 ((val) [all...]
/linux-master/include/asm-generic/
H A D	percpu.h	70 #define raw_cpu_generic_to_op(pcp, val, op) \ 72 *raw_cpu_ptr(&(pcp)) op val; \ 75 #define raw_cpu_generic_add_return(pcp, val) \ 79 *__p += val; \ 152 #define this_cpu_generic_to_op(pcp, val, op) \ 156 raw_cpu_generic_to_op(pcp, val, op); \ 161 #define this_cpu_generic_add_return(pcp, val) \ 166 __ret = raw_cpu_generic_add_return(pcp, val); \ 215 #define raw_cpu_write_1(pcp, val) raw_cpu_generic_to_op(pcp, val, [all...]
/linux-master/drivers/misc/
H A D	isl29020.c	28 int val; local 30 val = i2c_smbus_read_byte_data(client, 0x00); 32 if (val < 0) 33 return val; 34 return sprintf(buf, "%d000\n", 1 << (2 * (val & 3))); 42 int ret_val, val; local 66 val = i2c_smbus_read_byte_data(client, 0x00); 68 if (val < 0) 69 return val; 70 lux = ((((1 << (2 * (val 79 unsigned long val; local [all...]
/linux-master/drivers/phy/tegra/
H A D	phy-tegra194-p2u.c	58 u32 val; local 61 val = p2u_readl(phy, P2U_CONTROL_CMN); 62 val |= P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN; 63 p2u_writel(phy, val, P2U_CONTROL_CMN); 66 val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3); 67 val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN; 68 val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN; 69 p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN3); 71 val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN4); 72 val | 92 u32 val; local [all...]
/linux-master/drivers/input/misc/
H A D	iqs626a.c	468 unsigned int val; local 517 &val)) { 518 iqs626->kp_code[ch_id][i] = val; 522 &val)) { 524 val = EV_SW; 526 val = EV_KEY; 529 if (val != EV_KEY && val != EV_SW) { 532 val); 537 iqs626->kp_type[ch_id][i] = val; 591 unsigned int val; local 670 unsigned int val[IQS626_NUM_CRx_TX]; local 721 unsigned int val; local 888 unsigned int val; local 1237 unsigned int val; local 1709 unsigned int val; local 1768 unsigned int val; local [all...]
/linux-master/drivers/accel/ivpu/
H A D	ivpu_hw_40xx.c	170 u32 val; local 178 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0); 179 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val); 180 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val); 181 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, val); 183 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1); 184 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val); 277 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN); local 294 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN); local 311 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); local 321 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN); local 331 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY); local 341 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); local 352 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN); local 363 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY); local 374 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN); local 410 u32 val; local 447 u32 val; local 479 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); local 494 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0); local 518 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0); local 530 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES); local 541 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV); local 555 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN); local 565 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY); local 608 u32 val; local 638 u32 val; local 664 u32 val; local 747 u32 val; local 815 u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS); local 833 u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS); local 901 u32 val; local 946 u32 val; local 1006 u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET); local [all...]
/linux-master/sound/pci/lola/
H A D	lola_proc.c	19 unsigned int val; local 21 lola_read_param(chip, nid, LOLA_PAR_AUDIO_WIDGET_CAP, &val); 22 snd_iprintf(buffer, "Node 0x%02x %s wcaps 0x%x\n", nid, name, val); 23 lola_read_param(chip, nid, LOLA_PAR_STREAM_FORMATS, &val); 24 snd_iprintf(buffer, " Formats: 0x%x\n", val); 31 unsigned int val; local 33 lola_read_param(chip, nid, LOLA_PAR_AUDIO_WIDGET_CAP, &val); 34 snd_iprintf(buffer, "Node 0x%02x %s wcaps 0x%x\n", nid, name, val); 35 if (val == 0x00400200) 37 lola_read_param(chip, nid, ampcap, &val); 52 unsigned int val; local 91 unsigned int val; local 101 unsigned int val; local [all...]
/linux-master/drivers/clk/tegra/
H A D	clk-tegra20-emc.c	58 u32 val, div; local 60 val = readl_relaxed(emc->reg); 61 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK; 76 u32 val, div; local 78 val = readl_relaxed(emc->reg); 79 val &= ~CLK_SOURCE_EMC_2X_CLK_SRC_MASK; 80 val |= index << CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT; 82 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK; 85 val |= USE_PLLM_UD; 87 val 106 u32 val, div; local 139 u32 val, div; local [all...]
/linux-master/drivers/gpu/drm/msm/dsi/
H A D	dsi_phy_28nm.xml.h	97 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) argument 99 return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; 105 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) argument 107 return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; 113 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) argument 115 return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; 124 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) argument 126 return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; 132 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) argument 134 return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIF 140 DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) argument 148 DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) argument 156 DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) argument 164 DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) argument 170 DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) argument 178 DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) argument 186 DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) argument 273 DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) argument 282 DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) argument 288 DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) argument 296 DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) argument 304 DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) argument [all...]

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Indexes created Fri Apr 26 00:00:17 MDT 2024