1#ifndef ADRENO_COMMON_XML 2#define ADRENO_COMMON_XML 3 4/* Autogenerated file, DO NOT EDIT manually! 5 6This file was generated by the rules-ng-ng gen_header.py tool in this git repository: 7http://gitlab.freedesktop.org/mesa/mesa/ 8git clone https://gitlab.freedesktop.org/mesa/mesa.git 9 10The rules-ng-ng source files this header was generated from are: 11 12- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) 13*/ 14 15#ifdef __KERNEL__ 16#include <linux/bug.h> 17#define assert(x) BUG_ON(!(x)) 18#else 19#include <assert.h> 20#endif 21 22#ifdef __cplusplus 23#define __struct_cast(X) 24#else 25#define __struct_cast(X) (struct X) 26#endif 27 28enum chip { 29 A2XX = 2, 30 A3XX = 3, 31 A4XX = 4, 32 A5XX = 5, 33 A6XX = 6, 34 A7XX = 7, 35}; 36 37enum adreno_pa_su_sc_draw { 38 PC_DRAW_POINTS = 0, 39 PC_DRAW_LINES = 1, 40 PC_DRAW_TRIANGLES = 2, 41}; 42 43enum adreno_compare_func { 44 FUNC_NEVER = 0, 45 FUNC_LESS = 1, 46 FUNC_EQUAL = 2, 47 FUNC_LEQUAL = 3, 48 FUNC_GREATER = 4, 49 FUNC_NOTEQUAL = 5, 50 FUNC_GEQUAL = 6, 51 FUNC_ALWAYS = 7, 52}; 53 54enum adreno_stencil_op { 55 STENCIL_KEEP = 0, 56 STENCIL_ZERO = 1, 57 STENCIL_REPLACE = 2, 58 STENCIL_INCR_CLAMP = 3, 59 STENCIL_DECR_CLAMP = 4, 60 STENCIL_INVERT = 5, 61 STENCIL_INCR_WRAP = 6, 62 STENCIL_DECR_WRAP = 7, 63}; 64 65enum adreno_rb_blend_factor { 66 FACTOR_ZERO = 0, 67 FACTOR_ONE = 1, 68 FACTOR_SRC_COLOR = 4, 69 FACTOR_ONE_MINUS_SRC_COLOR = 5, 70 FACTOR_SRC_ALPHA = 6, 71 FACTOR_ONE_MINUS_SRC_ALPHA = 7, 72 FACTOR_DST_COLOR = 8, 73 FACTOR_ONE_MINUS_DST_COLOR = 9, 74 FACTOR_DST_ALPHA = 10, 75 FACTOR_ONE_MINUS_DST_ALPHA = 11, 76 FACTOR_CONSTANT_COLOR = 12, 77 FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, 78 FACTOR_CONSTANT_ALPHA = 14, 79 FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, 80 FACTOR_SRC_ALPHA_SATURATE = 16, 81 FACTOR_SRC1_COLOR = 20, 82 FACTOR_ONE_MINUS_SRC1_COLOR = 21, 83 FACTOR_SRC1_ALPHA = 22, 84 FACTOR_ONE_MINUS_SRC1_ALPHA = 23, 85}; 86 87enum adreno_rb_surface_endian { 88 ENDIAN_NONE = 0, 89 ENDIAN_8IN16 = 1, 90 ENDIAN_8IN32 = 2, 91 ENDIAN_16IN32 = 3, 92 ENDIAN_8IN64 = 4, 93 ENDIAN_8IN128 = 5, 94}; 95 96enum adreno_rb_dither_mode { 97 DITHER_DISABLE = 0, 98 DITHER_ALWAYS = 1, 99 DITHER_IF_ALPHA_OFF = 2, 100}; 101 102enum adreno_rb_depth_format { 103 DEPTHX_16 = 0, 104 DEPTHX_24_8 = 1, 105 DEPTHX_32 = 2, 106}; 107 108enum adreno_rb_copy_control_mode { 109 RB_COPY_RESOLVE = 1, 110 RB_COPY_CLEAR = 2, 111 RB_COPY_DEPTH_STENCIL = 5, 112}; 113 114enum a3xx_rop_code { 115 ROP_CLEAR = 0, 116 ROP_NOR = 1, 117 ROP_AND_INVERTED = 2, 118 ROP_COPY_INVERTED = 3, 119 ROP_AND_REVERSE = 4, 120 ROP_INVERT = 5, 121 ROP_XOR = 6, 122 ROP_NAND = 7, 123 ROP_AND = 8, 124 ROP_EQUIV = 9, 125 ROP_NOOP = 10, 126 ROP_OR_INVERTED = 11, 127 ROP_COPY = 12, 128 ROP_OR_REVERSE = 13, 129 ROP_OR = 14, 130 ROP_SET = 15, 131}; 132 133enum a3xx_render_mode { 134 RB_RENDERING_PASS = 0, 135 RB_TILING_PASS = 1, 136 RB_RESOLVE_PASS = 2, 137 RB_COMPUTE_PASS = 3, 138}; 139 140enum a3xx_msaa_samples { 141 MSAA_ONE = 0, 142 MSAA_TWO = 1, 143 MSAA_FOUR = 2, 144 MSAA_EIGHT = 3, 145}; 146 147enum a3xx_threadmode { 148 MULTI = 0, 149 SINGLE = 1, 150}; 151 152enum a3xx_instrbuffermode { 153 CACHE = 0, 154 BUFFER = 1, 155}; 156 157enum a3xx_threadsize { 158 TWO_QUADS = 0, 159 FOUR_QUADS = 1, 160}; 161 162enum a3xx_color_swap { 163 WZYX = 0, 164 WXYZ = 1, 165 ZYXW = 2, 166 XYZW = 3, 167}; 168 169enum a3xx_rb_blend_opcode { 170 BLEND_DST_PLUS_SRC = 0, 171 BLEND_SRC_MINUS_DST = 1, 172 BLEND_DST_MINUS_SRC = 2, 173 BLEND_MIN_DST_SRC = 3, 174 BLEND_MAX_DST_SRC = 4, 175}; 176 177enum a4xx_tess_spacing { 178 EQUAL_SPACING = 0, 179 ODD_SPACING = 2, 180 EVEN_SPACING = 3, 181}; 182 183enum a5xx_address_mode { 184 ADDR_32B = 0, 185 ADDR_64B = 1, 186}; 187 188enum a5xx_line_mode { 189 BRESENHAM = 0, 190 RECTANGULAR = 1, 191}; 192 193enum a6xx_tex_prefetch_cmd { 194 TEX_PREFETCH_UNK0 = 0, 195 TEX_PREFETCH_SAM = 1, 196 TEX_PREFETCH_GATHER4R = 2, 197 TEX_PREFETCH_GATHER4G = 3, 198 TEX_PREFETCH_GATHER4B = 4, 199 TEX_PREFETCH_GATHER4A = 5, 200 TEX_PREFETCH_UNK6 = 6, 201 TEX_PREFETCH_UNK7 = 7, 202}; 203 204#define REG_AXXX_CP_RB_BASE 0x000001c0 205 206#define REG_AXXX_CP_RB_CNTL 0x000001c1 207#define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f 208#define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 209static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) 210{ 211 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; 212} 213#define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 214#define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 215static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) 216{ 217 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; 218} 219#define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 220#define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 221static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) 222{ 223 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; 224} 225#define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 226#define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 227#define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 228 229#define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 230#define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 231#define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 232static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) 233{ 234 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; 235} 236#define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc 237#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 238static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) 239{ 240 assert(!(val & 0x3)); 241 return (((val >> 2)) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; 242} 243 244#define REG_AXXX_CP_RB_RPTR 0x000001c4 245 246#define REG_AXXX_CP_RB_WPTR 0x000001c5 247 248#define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 249 250#define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 251 252#define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 253 254#define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 255#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f 256#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 257static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) 258{ 259 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; 260} 261#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 262#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 263static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) 264{ 265 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; 266} 267#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 268#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 269static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) 270{ 271 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; 272} 273 274#define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 275#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 276#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 277static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) 278{ 279 return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; 280} 281#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 282#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 283static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) 284{ 285 return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; 286} 287 288#define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 289#define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f 290#define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 291static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) 292{ 293 return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; 294} 295#define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 296#define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 297static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) 298{ 299 return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; 300} 301#define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 302#define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 303static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) 304{ 305 return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; 306} 307 308#define REG_AXXX_CP_STQ_AVAIL 0x000001d8 309#define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f 310#define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 311static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) 312{ 313 return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; 314} 315 316#define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 317#define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f 318#define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 319static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) 320{ 321 return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; 322} 323 324#define REG_AXXX_SCRATCH_UMSK 0x000001dc 325#define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff 326#define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 327static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) 328{ 329 return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; 330} 331#define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 332#define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 333static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) 334{ 335 return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; 336} 337 338#define REG_AXXX_SCRATCH_ADDR 0x000001dd 339 340#define REG_AXXX_CP_ME_RDADDR 0x000001ea 341 342#define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec 343 344#define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed 345 346#define REG_AXXX_CP_INT_CNTL 0x000001f2 347#define AXXX_CP_INT_CNTL_SW_INT_MASK 0x00080000 348#define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK 0x00800000 349#define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK 0x01000000 350#define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK 0x02000000 351#define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK 0x04000000 352#define AXXX_CP_INT_CNTL_IB_ERROR_MASK 0x08000000 353#define AXXX_CP_INT_CNTL_IB2_INT_MASK 0x20000000 354#define AXXX_CP_INT_CNTL_IB1_INT_MASK 0x40000000 355#define AXXX_CP_INT_CNTL_RB_INT_MASK 0x80000000 356 357#define REG_AXXX_CP_INT_STATUS 0x000001f3 358 359#define REG_AXXX_CP_INT_ACK 0x000001f4 360 361#define REG_AXXX_CP_ME_CNTL 0x000001f6 362#define AXXX_CP_ME_CNTL_BUSY 0x20000000 363#define AXXX_CP_ME_CNTL_HALT 0x10000000 364 365#define REG_AXXX_CP_ME_STATUS 0x000001f7 366 367#define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 368 369#define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 370 371#define REG_AXXX_CP_ME_RAM_DATA 0x000001fa 372 373#define REG_AXXX_CP_DEBUG 0x000001fc 374#define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 375#define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 376#define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 377#define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 378#define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 379#define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 380#define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 381#define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 382 383#define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd 384#define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f 385#define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 386static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) 387{ 388 return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; 389} 390#define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 391#define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 392static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) 393{ 394 return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; 395} 396 397#define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe 398#define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f 399#define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 400static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) 401{ 402 return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; 403} 404#define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 405#define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 406static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) 407{ 408 return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; 409} 410 411#define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff 412#define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f 413#define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 414static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) 415{ 416 return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; 417} 418#define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 419#define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 420static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) 421{ 422 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; 423} 424 425#define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 426 427#define REG_AXXX_CP_STQ_ST_STAT 0x00000443 428 429#define REG_AXXX_CP_ST_BASE 0x0000044d 430 431#define REG_AXXX_CP_ST_BUFSZ 0x0000044e 432 433#define REG_AXXX_CP_MEQ_STAT 0x0000044f 434 435#define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 436 437#define REG_AXXX_CP_BIN_MASK_LO 0x00000454 438 439#define REG_AXXX_CP_BIN_MASK_HI 0x00000455 440 441#define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 442 443#define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 444 445#define REG_AXXX_CP_IB1_BASE 0x00000458 446 447#define REG_AXXX_CP_IB1_BUFSZ 0x00000459 448 449#define REG_AXXX_CP_IB2_BASE 0x0000045a 450 451#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b 452 453#define REG_AXXX_CP_STAT 0x0000047f 454#define AXXX_CP_STAT_CP_BUSY 0x80000000 455#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000 456#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000 457#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000 458#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000 459#define AXXX_CP_STAT_ME_BUSY 0x04000000 460#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000 461#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000 462#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000 463#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000 464#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000 465#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000 466#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000 467#define AXXX_CP_STAT_PFP_BUSY 0x00020000 468#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000 469#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000 470#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000 471#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800 472#define AXXX_CP_STAT_CSF_BUSY 0x00000400 473#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200 474#define AXXX_CP_STAT_EVENT_BUSY 0x00000100 475#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080 476#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040 477#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020 478#define AXXX_CP_STAT_RCIU_BUSY 0x00000010 479#define AXXX_CP_STAT_RBIU_BUSY 0x00000008 480#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004 481#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002 482#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001 483 484#define REG_AXXX_CP_SCRATCH_REG0 0x00000578 485 486#define REG_AXXX_CP_SCRATCH_REG1 0x00000579 487 488#define REG_AXXX_CP_SCRATCH_REG2 0x0000057a 489 490#define REG_AXXX_CP_SCRATCH_REG3 0x0000057b 491 492#define REG_AXXX_CP_SCRATCH_REG4 0x0000057c 493 494#define REG_AXXX_CP_SCRATCH_REG5 0x0000057d 495 496#define REG_AXXX_CP_SCRATCH_REG6 0x0000057e 497 498#define REG_AXXX_CP_SCRATCH_REG7 0x0000057f 499 500#define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 501 502#define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 503 504#define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 505 506#define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 507 508#define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 509 510#define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 511 512#define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 513 514#define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 515 516#define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 517 518#define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 519 520#define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a 521 522#define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b 523 524#define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c 525 526#define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d 527 528#define REG_AXXX_CP_ME_NRT_DATA 0x0000060e 529 530#define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 531 532#define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 533 534#define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 535 536#ifdef __cplusplus 537#endif 538 539#endif /* ADRENO_COMMON_XML */ 540