/linux-master/drivers/pinctrl/spear/ |
H A D | pinctrl-spear1310.c | 241 .mask = PMX_I2C0_MASK, 245 .mask = PMX_I2C0_MASK, 277 .mask = PMX_SSP0_MASK, 281 .mask = PMX_SSP0_MASK, 306 .mask = PMX_SSP0_CS0_MASK, 310 .mask = PMX_SSP0_CS0_MASK, 335 .mask = PMX_SSP0_CS1_2_MASK, 339 .mask = PMX_SSP0_CS1_2_MASK, 372 .mask = PMX_I2S0_MASK, 376 .mask [all...] |
/linux-master/drivers/net/ethernet/pensando/ionic/ |
H A D | ionic_regs.h | 11 * @mask: interrupt mask value. 13 * @mask_assert: interrupt mask value on assert. 18 u32 mask; member in struct:ionic_intr 28 /** enum ionic_intr_mask_vals - valid values for mask and mask_assert. 30 * @IONIC_INTR_MASK_SET: mask interrupt. 38 * @IONIC_INTR_CRED_COUNT: bit mask of credit count, no shift needed. 39 * @IONIC_INTR_CRED_COUNT_SIGNED: bit mask of credit count, including sign bit. 60 int intr_idx, u32 mask) 62 iowrite32(mask, 59 ionic_intr_mask(struct ionic_intr __iomem *intr_ctrl, int intr_idx, u32 mask) argument 87 ionic_intr_mask_assert(struct ionic_intr __iomem *intr_ctrl, int intr_idx, u32 mask) argument [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ |
H A D | g94.c | 41 g94_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) argument 47 inte0 = (inte0 & ~(mask << 16)) | (data << 16); 49 inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff); 50 mask >>= 16; 53 inte1 = (inte1 & ~(mask << 16)) | (data << 16); 55 inte1 = (inte1 & ~mask) | data;
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H A D | gk104.c | 43 gk104_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) argument 49 inte0 = (inte0 & ~(mask << 16)) | (data << 16); 51 inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff); 52 mask >>= 16; 55 inte1 = (inte1 & ~(mask << 16)) | (data << 16); 57 inte1 = (inte1 & ~mask) | data;
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H A D | nv10.c | 55 u32 reg, mask, data; local 60 mask = 0x00000011; 66 mask = 0x00000003; 72 mask = 0x00000003; 78 nvkm_mask(device, reg, mask << line, data << line); 94 nv10_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) argument 99 inte = (inte & ~(mask << 16)) | (data << 16); 101 inte = (inte & ~mask) | data;
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/linux-master/drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
H A D | timer.h | 69 #define nvkm_wait_nsec(d,n,addr,mask,data) \ 71 if ((nvkm_rd32(d, (addr)) & (mask)) == (data)) \ 74 #define nvkm_wait_usec(d,u,addr,mask,data) \ 75 nvkm_wait_nsec((d), (u) * 1000, (addr), (mask), (data)) 76 #define nvkm_wait_msec(d,m,addr,mask,data) \ 77 nvkm_wait_usec((d), (m) * 1000, (addr), (mask), (data))
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/linux-master/arch/arm/lib/ |
H A D | backtrace-clang.S | 18 #define mask r7 define 105 moveq mask, #0xfc000003 106 movne mask, #0 @ mask for 32-bit 112 for_each_frame: tst frame, mask @ Check for address exceptions 127 teq sv_fp, mask @ make sure next frame exists 162 bic sv_pc, sv_pc, mask @ mask PC/LR for the mode 171 bic r1, r1, mask @ mask P [all...] |
/linux-master/arch/powerpc/platforms/powermac/ |
H A D | pfunc_base.c | 44 static int macio_do_gpio_write(PMF_STD_ARGS, u8 value, u8 mask) argument 57 tmp = (tmp & ~mask) | (value & mask); 66 static int macio_do_gpio_read(PMF_STD_ARGS, u8 mask, int rshift, u8 xor) argument 76 *args->u[0].p = ((value & mask) >> rshift) ^ xor; 146 static int macio_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask) argument 152 MACIO_OUT32(offset, (MACIO_IN32(offset) & ~mask) | (value & mask)); 169 static int macio_do_write_reg8(PMF_STD_ARGS, u32 offset, u8 value, u8 mask) argument 175 MACIO_OUT8(offset, (MACIO_IN8(offset) & ~mask) | (valu 192 macio_do_read_reg32_msrx(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift, u32 xor) argument 205 macio_do_read_reg8_msrx(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift, u32 xor) argument 218 macio_do_write_reg32_slm(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask) argument 238 macio_do_write_reg8_slm(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask) argument 280 unin_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask) argument [all...] |
/linux-master/fs/coda/ |
H A D | cache.c | 31 void coda_cache_enter(struct inode *inode, int mask) argument 39 cii->c_cached_perm = mask; 41 cii->c_cached_perm |= mask; 61 /* check if the mask has been matched against the acl already */ 62 int coda_cache_check(struct inode *inode, int mask) argument 68 hit = (mask & cii->c_cached_perm) == mask &&
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/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_engine_pm.h | 44 intel_engine_mask_t tmp, mask = engine->mask; local 46 for_each_engine_masked(tengine, gt, mask, tmp) 80 intel_engine_mask_t tmp, mask = engine->mask; local 82 for_each_engine_masked(tengine, gt, mask, tmp)
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/linux-master/drivers/power/reset/ |
H A D | syscon-poweroff.c | 23 u32 mask; member in struct:syscon_poweroff_data 31 regmap_update_bits(data->map, data->offset, data->mask, data->value); 65 mask_err = of_property_read_u32(dev->of_node, "mask", &data->mask); 67 dev_err(dev, "unable to read 'value' and 'mask'"); 73 data->value = data->mask; 74 data->mask = 0xFFFFFFFF; 76 /* support value without mask*/ 77 data->mask = 0xFFFFFFFF;
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/linux-master/drivers/net/ethernet/marvell/prestera/ |
H A D | prestera_flower.c | 148 __be16 key, mask; local 152 if (match.mask->l2_miss) { 157 if (match.mask->ingress_ifindex != 0xFFFFFFFF) { 159 "Unsupported ingress ifindex mask"); 178 mask = htons(0x1FFF << 3); 181 rule_match_set(r_match->mask, SYS_PORT, mask); 183 mask = htons(0x3FF); 186 rule_match_set(r_match->mask, SYS_DEV, mask); 343 __be16 mask = cpu_to_be16(match.mask->vlan_id); local [all...] |
/linux-master/arch/alpha/include/asm/ |
H A D | special_insns.h | 37 #define amask(mask) \ 38 ({ unsigned long __amask, __input = (mask); \
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/linux-master/drivers/net/ethernet/smsc/ |
H A D | smc9194.h | 211 /* this enables an interrupt in the interrupt mask register */ 213 unsigned char mask;\ 215 mask = inb( ioaddr + INT_MASK );\ 216 mask |= (x);\ 217 outb( mask, ioaddr + INT_MASK ); \ 220 /* this disables an interrupt from the interrupt mask register */ 223 unsigned char mask;\ 225 mask = inb( ioaddr + INT_MASK );\ 226 mask &= ~(x);\ 227 outb( mask, ioadd [all...] |
/linux-master/include/linux/dma/ |
H A D | qcom_bam_dma.h | 18 * @mask - register mask. 25 __le32 mask; member in struct:bam_cmd_element 53 bam_ce->mask = cpu_to_le32(0xffffffff);
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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
H A D | ramfuc.h | 18 u32 mask; member in struct:ramfuc_reg 23 ramfuc_stride(u32 addr, u32 stride, u32 mask) argument 29 .mask = mask, 41 .mask = 0x3, 53 .mask = 0x1, 93 unsigned int mask, off = 0; local 98 for (mask = reg->mask; mask > 112 ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data) argument 123 ramfuc_wait(struct ramfuc *ram, u32 addr, u32 mask, u32 data, u32 nsec) argument [all...] |
/linux-master/drivers/staging/sm750fb/ |
H A D | sm750_cursor.h | 12 const u8 *data, const u8 *mask); 14 const u8 *data, const u8 *mask);
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/linux-master/arch/alpha/kernel/ |
H A D | sys_sable.c | 39 /* Note mask bit is true for DISABLED irqs. */ 42 void (*update_irq_hw)(unsigned long bit, unsigned long mask); 93 sable_update_irq_hw(unsigned long bit, unsigned long mask) argument 99 mask >>= 16; 102 mask >>= 8; 105 outb(mask, port); 143 34, 33, 32, 12, 35, 36, 1, 6, /* mask 0-7 */ 144 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */ 145 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */ 292 lynx_update_irq_hw(unsigned long bit, unsigned long mask) argument 447 unsigned long bit, mask; local 463 unsigned long bit, mask; local 479 unsigned long bit, mask; local [all...] |
/linux-master/drivers/staging/media/atomisp/pci/mmu/ |
H A D | sh_mmu_mrfld.c | 40 unsigned int mask = mmu->driver->pte_valid_mask; local 42 return (phys_addr_t)((pte & ~mask) << ISP_PAGE_OFFSET);
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | common_baco.h | 39 uint32_t mask; member in struct:baco_cmd_entry 51 uint32_t mask; member in struct:soc15_baco_cmd_entry
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/linux-master/include/linux/ |
H A D | align.h | 10 #define __ALIGN_MASK(x, mask) __ALIGN_KERNEL_MASK((x), (mask))
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/linux-master/drivers/char/ipmi/ |
H A D | kcs_bmc_device.h | 12 void (*irq_mask_update)(struct kcs_bmc_device *kcs_bmc, u8 mask, u8 enable); 15 void (*io_updateb)(struct kcs_bmc_device *kcs_bmc, u32 reg, u8 mask, u8 b);
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/linux-master/drivers/memory/tegra/ |
H A D | tegra210.c | 27 .mask = 0xff, 43 .mask = 0xff, 59 .mask = 0xff, 75 .mask = 0xff, 91 .mask = 0xff, 107 .mask = 0xff, 123 .mask = 0xff, 139 .mask = 0xff, 155 .mask = 0xff, 171 .mask [all...] |
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | mmsch_v1_0.h | 110 uint32_t mask, uint32_t data) 113 direct_rd_mod_wt->mask_value = mask; 122 uint32_t mask, uint32_t wait) 125 direct_poll->mask_value = mask; 130 #define MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \ 133 (mask), (data)); \ 146 #define MMSCH_V1_0_INSERT_DIRECT_POLL(reg, mask, wait) { \ 149 (mask), (wait)); \ 107 mmsch_v1_0_insert_direct_rd_mod_wt(struct mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt, uint32_t *init_table, uint32_t reg_offset, uint32_t mask, uint32_t data) argument 119 mmsch_v1_0_insert_direct_poll(struct mmsch_v1_0_cmd_direct_polling *direct_poll, uint32_t *init_table, uint32_t reg_offset, uint32_t mask, uint32_t wait) argument
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/linux-master/arch/powerpc/perf/ |
H A D | callchain.h | 12 unsigned long mask = is_32bit_task() ? 3 : 7; local 15 return (!sp || (sp & mask) || (sp > top));
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