Searched refs:base (Results 276 - 300 of 6511) sorted by relevance

<<11121314151617181920>>

/linux-master/drivers/gpu/drm/i915/gt/
H A Dgen6_ppgtt.c23 dma_addr_t addr = pt ? px_dma(pt) : px_dma(ppgtt->base.vm.scratch[1]);
86 i915_pt_entry(ppgtt->base.pd, pde++);
152 struct i915_page_directory * const pd = ppgtt->base.pd;
166 gen6_ggtt_invalidate(ppgtt->base.vm.gt->ggtt);
177 struct i915_page_directory * const pd = ppgtt->base.pd;
191 __i915_gem_object_pin_pages(pt->base);
221 struct i915_address_space * const vm = &ppgtt->base.vm;
258 struct i915_page_directory * const pd = ppgtt->base.pd;
264 free_pt(&ppgtt->base.vm, pt);
274 if (ppgtt->base
324 gen6_ppgtt_pin(struct i915_ppgtt *base, struct i915_gem_ww_ctx *ww) argument
419 gen6_ppgtt_unpin(struct i915_ppgtt *base) argument
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
H A Dnv50.c24 #define nv50_instmem(p) container_of((p), struct nv50_instmem, base)
34 struct nvkm_instmem base; member in struct:nv50_instmem
44 #define nv50_instobj(p) container_of((p), struct nv50_instobj, base.memory)
47 struct nvkm_instobj base; member in struct:nv50_instobj
61 struct nvkm_device *device = imem->base.subdev.device;
62 u64 base = (nvkm_memory_addr(iobj->ram) + offset) & 0xffffff00000ULL; local
66 spin_lock_irqsave(&imem->base.lock, flags);
67 if (unlikely(imem->addr != base)) {
68 nvkm_wr32(device, 0x001700, base >> 16);
69 imem->addr = base;
81 u64 base = (nvkm_memory_addr(iobj->ram) + offset) & 0xffffff00000ULL; local
357 nv50_instobj_wrap(struct nvkm_instmem *base, struct nvkm_memory *memory, struct nvkm_memory **pmemory) argument
398 nv50_instmem_fini(struct nvkm_instmem *base) argument
404 nv50_instmem_dtor(struct nvkm_instmem *base) argument
[all...]
/linux-master/arch/arm/crypto/
H A Dchacha-glue.c197 .base.cra_name = "chacha20",
198 .base.cra_driver_name = "chacha20-arm",
199 .base.cra_priority = 200,
200 .base.cra_blocksize = 1,
201 .base.cra_ctxsize = sizeof(struct chacha_ctx),
202 .base.cra_module = THIS_MODULE,
212 .base.cra_name = "xchacha20",
213 .base.cra_driver_name = "xchacha20-arm",
214 .base.cra_priority = 200,
215 .base
[all...]
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_plane_initial.c23 struct drm_i915_private *i915 = to_i915(this->base.dev);
28 to_intel_plane(crtc->base.primary);
30 to_intel_plane_state(plane->base.state);
32 to_intel_crtc_state(crtc->base.state);
40 if (plane_configs[this->pipe].base == plane_configs[crtc->pipe].base) {
58 u32 base; local
60 base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
62 gte += base / I915_GTT_PAGE_SIZ
109 u32 base; local
146 u32 base, size; local
[all...]
/linux-master/drivers/iommu/
H A Dmsm_iommu.c78 static void msm_iommu_reset(void __iomem *base, int ncb) argument
82 SET_RPUE(base, 0);
83 SET_RPUEIE(base, 0);
84 SET_ESRRESTORE(base, 0);
85 SET_TBE(base, 0);
86 SET_CR(base, 0);
87 SET_SPDMBE(base, 0);
88 SET_TESTBUSCR(base, 0);
89 SET_TLBRSW(base, 0);
90 SET_GLOBAL_TLBIALL(base,
235 __reset_context(void __iomem *base, int ctx) argument
257 __program_context(void __iomem *base, int ctx, struct msm_priv *priv) argument
574 print_ctx_regs(void __iomem *base, int ctx) argument
[all...]
/linux-master/crypto/
H A Dchacha_generic.c71 .base.cra_name = "chacha20",
72 .base.cra_driver_name = "chacha20-generic",
73 .base.cra_priority = 100,
74 .base.cra_blocksize = 1,
75 .base.cra_ctxsize = sizeof(struct chacha_ctx),
76 .base.cra_module = THIS_MODULE,
86 .base.cra_name = "xchacha20",
87 .base.cra_driver_name = "xchacha20-generic",
88 .base.cra_priority = 100,
89 .base
[all...]
/linux-master/arch/mips/crypto/
H A Dchacha-glue.c82 .base.cra_name = "chacha20",
83 .base.cra_driver_name = "chacha20-mips",
84 .base.cra_priority = 200,
85 .base.cra_blocksize = 1,
86 .base.cra_ctxsize = sizeof(struct chacha_ctx),
87 .base.cra_module = THIS_MODULE,
97 .base.cra_name = "xchacha20",
98 .base.cra_driver_name = "xchacha20-mips",
99 .base.cra_priority = 200,
100 .base
[all...]
/linux-master/arch/arm/include/asm/
H A Dvfpmacros.h31 .macro VFPFLDMIA, base, tmp variable
34 fldmiax \base!, {d0-d15}
36 vldmia \base!, {d0-d15}
44 vldmiane \base!, {d16-d31} variable
45 addeq \base, \base, #32*4 @ step over unused register space variable
50 vldmiaeq \base!, {d16-d31}
51 addne \base, \base, #32*4 @ step over unused register space
57 .macro VFPFSTMIA, base, tm variable
59 fstmiax \\base!, {d0-d15} variable
69 vstmiane \\base!, {d16-d31} variable
70 addeq \\base, \\base, #32*4 @ step over unused register space variable
[all...]
/linux-master/drivers/media/platform/qcom/camss/
H A Dcamss-csiphy-2ph-1-0.c46 u8 hw_version = readl_relaxed(csiphy->base +
58 writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
60 writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
108 writel_relaxed(0x1, csiphy->base +
110 writel_relaxed(0x1, csiphy->base +
115 writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);
118 writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
126 writel_relaxed(0x10, csiphy->base +
128 writel_relaxed(settle_cnt, csiphy->base +
130 writel_relaxed(0x3f, csiphy->base
[all...]
/linux-master/drivers/s390/block/
H A Ddasd_genhd.c48 struct dasd_device *base; local
52 base = block->base;
53 if (base->devindex >= DASD_PER_MAJOR)
75 gdp->first_minor = base->devindex << DASD_PARTN_BITS;
87 if (base->devindex > 25) {
88 if (base->devindex > 701) {
89 if (base->devindex > 18277)
91 'a'+(((base->devindex-18278)
94 'a'+(((base
[all...]
/linux-master/drivers/acpi/acpica/
H A Dutstrtoul64.c20 * 1) A standard strtoul() function that supports 64-bit integers, base
84 u32 base = 10; /* Default is decimal */ local
101 * 1) Check for a hex constant. A "0x" prefix indicates base 16.
104 base = 16;
112 base = 8;
128 * Perform the base 8, 10, or 16 conversion. A 64-bit numeric overflow
131 switch (base) {
251 * Base is either 10 (default) or 16 (with 0x prefix). Octal (base 8) strings
290 u32 base = 10; /* Default is decimal */ local
303 base
[all...]
/linux-master/drivers/clocksource/
H A Darmv7m_systick.c28 void __iomem *base; local
32 base = of_iomap(np, 0);
33 if (!base) {
34 pr_warn("system-timer: invalid base address\n");
57 writel_relaxed(SYSTICK_LOAD_RELOAD_MASK, base + SYST_RVR);
58 writel_relaxed(SYST_CSR_ENABLE, base + SYST_CSR);
60 ret = clocksource_mmio_init(base + SYST_CVR, "arm_system_timer", rate,
79 iounmap(base);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_ipp.c38 ippn10->base.ctx
66 ippn10->base.ctx = ctx;
67 ippn10->base.inst = inst;
68 ippn10->base.funcs = &dcn10_ipp_funcs;
83 ippn10->base.ctx = ctx;
84 ippn10->base.inst = inst;
85 ippn10->base.funcs = &dcn20_ipp_funcs;
/linux-master/drivers/gpio/
H A Dgpio-rda.c39 void __iomem *base; member in struct:rda_gpio
48 void __iomem *base = rda_gpio->base; local
53 tmp = readl_relaxed(base + reg);
60 writel_relaxed(tmp, base + reg);
68 void __iomem *base = rda_gpio->base; local
75 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
91 void __iomem *base = rda_gpio->base; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hpo_dp_link_encoder.c32 enc3->base.ctx->logger
42 enc3->base.ctx
79 enc31->base.ctx = ctx;
81 enc31->base.inst = inst;
82 enc31->base.funcs = &dcn32_hpo_dp_link_encoder_funcs;
83 enc31->base.hpd_source = HPD_SOURCEID_UNKNOWN;
84 enc31->base.transmitter = TRANSMITTER_UNKNOWN;
/linux-master/drivers/clk/qcom/
H A Dkpss-xcc.c35 void __iomem *base; local
39 base = devm_platform_ioremap_resource(pdev, 0);
40 if (IS_ERR(base))
41 return PTR_ERR(base);
48 base += 0x14;
51 base += 0x28;
56 base, 0, 0x3,
/linux-master/drivers/gpu/drm/ast/
H A Dast_mm.c76 struct drm_device *dev = &ast->base;
78 resource_size_t base, size; local
81 base = pci_resource_start(pdev, 0);
85 devm_arch_io_reserve_memtype_wc(dev->dev, base, size);
86 devm_arch_phys_wc_add(dev->dev, base, size);
90 ast->vram = devm_ioremap_wc(dev->dev, base, vram_size);
94 ast->vram_base = base;
/linux-master/drivers/misc/pvpanic/
H A Dpvpanic-mmio.c30 void __iomem *base; local
38 base = devm_ioport_map(dev, res->start, resource_size(res));
39 if (!base)
43 base = devm_ioremap_resource(dev, res);
44 if (IS_ERR(base))
45 return PTR_ERR(base);
51 return devm_pvpanic_probe(dev, base);
/linux-master/arch/arm/mach-omap2/
H A Dwd_timer.c33 void __iomem *base; local
40 base = omap_hwmod_get_mpu_rt_va(oh);
41 if (!base) {
42 pr_err("%s: Could not get the base address for %s\n",
48 writel_relaxed(0xAAAA, base + OMAP_WDT_SPR);
49 while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
52 writel_relaxed(0x5555, base + OMAP_WDT_SPR);
53 while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
/linux-master/arch/powerpc/kexec/
H A Dranges.c66 * @base: Base address of the range to add.
73 static int __add_mem_range(struct crash_mem **mem_ranges, u64 base, u64 size) argument
83 mem_rngs->ranges[mem_rngs->nr_ranges].start = base;
84 mem_rngs->ranges[mem_rngs->nr_ranges].end = base + size - 1;
86 base, base + size - 1, mem_rngs->nr_ranges);
201 * @base: Base address of the range to add.
208 int add_mem_range(struct crash_mem **mem_ranges, u64 base, u64 size) argument
217 end = base + size - 1;
220 return __add_mem_range(mem_ranges, base, siz
249 u64 base; local
284 u64 base, end; local
337 u32 base, size; local
362 u64 base, size; local
402 u64 base, size; local
[all...]
/linux-master/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_8_0_sc8280xp.h23 .base = 0x0, .len = 0x494,
42 .base = 0x15000, .len = 0x204,
47 .base = 0x16000, .len = 0x204,
52 .base = 0x17000, .len = 0x204,
57 .base = 0x18000, .len = 0x204,
62 .base = 0x19000, .len = 0x204,
67 .base = 0x1a000, .len = 0x204,
76 .base = 0x4000, .len = 0x2ac,
84 .base = 0x6000, .len = 0x2ac,
92 .base
[all...]
/linux-master/drivers/gpu/drm/lima/
H A Dlima_gem.c24 struct address_space *mapping = bo->base.base.filp->f_mapping;
25 struct device *dev = bo->base.base.dev->dev;
32 if (bo->heap_size >= bo->base.base.size)
35 new_size = min(new_size, bo->base.base.size);
37 dma_resv_lock(bo->base.base
[all...]
/linux-master/arch/arm/mm/
H A Dcache-l2x0.c65 static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) argument
67 if (val == readl_relaxed(base + reg))
72 writel_relaxed(val, base + reg);
80 static inline void l2c_set_debug(void __iomem *base, unsigned long val) argument
82 l2c_write_sec(val, base, L2X0_DEBUG_CTRL);
91 static inline void l2c_unlock(void __iomem *base, unsigned num) argument
96 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE +
98 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE +
103 static void l2c_configure(void __iomem *base) argument
105 l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTR
112 l2c_enable(void __iomem *base, unsigned num_lock) argument
134 void __iomem *base = l2x0_base; local
143 l2c_save(void __iomem *base) argument
150 void __iomem *base = l2x0_base; local
173 __l2c210_cache_sync(void __iomem *base) argument
189 void __iomem *base = l2x0_base; local
208 void __iomem *base = l2x0_base; local
217 void __iomem *base = l2x0_base; local
226 void __iomem *base = l2x0_base; local
268 __l2c220_cache_sync(void __iomem *base) argument
274 l2c220_op_way(void __iomem *base, unsigned reg) argument
309 void __iomem *base = l2x0_base; local
336 void __iomem *base = l2x0_base; local
355 void __iomem *base = l2x0_base; local
386 l2c220_enable(void __iomem *base, unsigned num_lock) argument
398 l2c220_unlock(void __iomem *base, unsigned num_lock) argument
469 void __iomem *base = l2x0_base; local
503 void __iomem *base = l2x0_base; local
528 void __iomem *base = l2x0_base; local
539 l2c310_save(void __iomem *base) argument
568 l2c310_configure(void __iomem *base) argument
607 l2c310_enable(void __iomem *base, unsigned num_lock) argument
681 l2c310_fixup(void __iomem *base, u32 cache_id, struct outer_cache_fns *fns) argument
754 l2c310_unlock(void __iomem *base, unsigned num_lock) argument
894 l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) argument
1378 void __iomem *base = l2x0_base; local
1428 void __iomem *base = l2x0_base; local
1446 void __iomem *base = l2x0_base; local
1457 aurora_save(void __iomem *base) argument
1467 aurora_enable_no_outer(void __iomem *base, unsigned num_lock) argument
1481 aurora_fixup(void __iomem *base, u32 cache_id, struct outer_cache_fns *fns) argument
1714 tauros3_save(void __iomem *base) argument
1724 tauros3_configure(void __iomem *base) argument
[all...]
/linux-master/drivers/gpu/drm/nouveau/
H A Dnv50_fence.c42 u32 limit = start + priv->bo->bo.base.size - 1;
49 nouveau_fence_context_new(chan, &fctx->base);
50 fctx->base.emit = nv10_fence_emit;
51 fctx->base.read = nv10_fence_read;
52 fctx->base.sync = nv17_fence_sync;
78 priv->base.dtor = nv10_fence_destroy;
79 priv->base.resume = nv17_fence_resume;
80 priv->base.context_new = nv50_fence_context_new;
81 priv->base.context_del = nv10_fence_context_del;
/linux-master/drivers/gpu/drm/sprd/
H A Dsprd_dpu.h35 * @base: DPU controller base address
46 void __iomem *base; member in struct:dpu_context
64 struct drm_crtc base; member in struct:sprd_dpu
71 return container_of(crtc, struct sprd_dpu, base);
77 u32 bits = readl_relaxed(ctx->base + offset);
79 writel(bits | set_bits, ctx->base + offset);
85 u32 bits = readl_relaxed(ctx->base + offset);
87 writel(bits & ~clr_bits, ctx->base + offset);
95 return readl(ctx->base
[all...]

Completed in 246 milliseconds

<<11121314151617181920>>