/linux-master/fs/ubifs/ |
H A D | lpt.c | 1880 * @rd: whether to initialize lpt for reading 1883 * For mounting 'rw', @rd and @wr are both true. For mounting 'ro', @rd is true 1884 * and @wr is false. For mounting from 'ro' to 'rw', @rd is false and @wr is 1889 int ubifs_lpt_init(struct ubifs_info *c, int rd, int wr) argument 1893 if (rd) { 1910 if (rd)
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/linux-master/fs/jffs2/ |
H A D | readinode.c | 587 struct jffs2_raw_dirent *rd, size_t read, 596 crc = crc32(0, rd, sizeof(*rd) - 8); 597 if (unlikely(crc != je32_to_cpu(rd->node_crc))) { 599 ref_offset(ref), je32_to_cpu(rd->node_crc), crc); 610 if (unlikely(PAD((rd->nsize + sizeof(*rd))) != PAD(je32_to_cpu(rd->totlen)))) { 612 ref_offset(ref), rd->nsize, je32_to_cpu(rd 586 read_direntry(struct jffs2_sb_info *c, struct jffs2_raw_node_ref *ref, struct jffs2_raw_dirent *rd, size_t read, struct jffs2_readinode_info *rii) argument 713 read_dnode(struct jffs2_sb_info *c, struct jffs2_raw_node_ref *ref, struct jffs2_raw_inode *rd, int rdlen, struct jffs2_readinode_info *rii) argument [all...] |
H A D | nodelist.h | 144 #define dirent_node_state(rd) ( (je32_to_cpu((rd)->ino)?REF_PRISTINE:REF_NORMAL) ) 402 struct jffs2_raw_dirent *rd, const unsigned char *name,
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/linux-master/drivers/net/wireless/quantenna/qtnfmac/ |
H A D | core.h | 108 struct ieee80211_regdomain *rd; member in struct:qtnf_wmac
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/linux-master/arch/arm/crypto/ |
H A D | aes-ce-core.S | 139 add ip, r2, #32 @ 3rd round key 146 add ip, r2, #32 @ 3rd round key 152 add ip, r2, #32 @ 3rd round key 158 add ip, r2, #32 @ 3rd round key 498 add ip, r6, #32 @ 3rd round key of key 2
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/linux-master/arch/arm/include/debug/ |
H A D | zynq.S | 32 .macro senduart,rd,rx 33 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA 36 .macro waituartcts,rd,rx 39 .macro waituarttxrdy,rd,rx 40 1001: ldr \rd, [\rx, #UART_SR_OFFSET] 41 ARM_BE8( rev \rd, \rd ) 42 tst \rd, #UART_SR_TXEMPTY 46 .macro busyuart,rd,rx 47 1002: ldr \rd, [\r [all...] |
H A D | vt8500.S | 21 .macro senduart,rd,rx 22 strb \rd, [\rx, #0] 25 .macro busyuart,rd,rx 26 1001: ldr \rd, [\rx, #0x1c] 27 ands \rd, \rd, #0x2 31 .macro waituartcts,rd,rx 34 .macro waituarttxrdy,rd,rx
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H A D | vf.S | 22 .macro senduart, rd, rx 23 strb \rd, [\rx, #0x7] @ Data Register 26 .macro busyuart, rd, rx 27 1001: ldrb \rd, [\rx, #0x4] @ Status Register 1 28 tst \rd, #1 << 6 @ TC 32 .macro waituartcts,rd,rx 35 .macro waituarttxrdy,rd,rx
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H A D | stm32.S | 26 .macro senduart,rd,rx 27 strb \rd, [\rx, #STM32_USART_TDR_OFF] 30 .macro waituartcts,rd,rx 33 .macro waituarttxrdy,rd,rx 34 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register 35 tst \rd, #STM32_USART_TXE @ TXE = 1 = tx empty 39 .macro busyuart,rd,rx 40 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register 41 tst \rd, #STM32_USART_TC @ TC = 1 = tx complete
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H A D | sa1100.S | 50 .macro senduart,rd,rx 51 str \rd, [\rx, #UTDR] 54 .macro waituartcts,rd,rx 57 .macro waituarttxrdy,rd,rx 58 1001: ldr \rd, [\rx, #UTSR1] 59 tst \rd, #UTSR1_TNF 63 .macro busyuart,rd,rx 64 1001: ldr \rd, [\rx, #UTSR1] 65 tst \rd, #UTSR1_TBY
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H A D | renesas-scif.S | 36 .macro waituartcts,rd,rx 39 .macro waituarttxrdy, rd, rx 40 1001: ldrh \rd, [\rx, #FSR] 41 tst \rd, #TDFE 45 .macro senduart, rd, rx 46 strb \rd, [\rx, #FTDR] 47 ldrh \rd, [\rx, #FSR] 48 bic \rd, \rd, #TEND 49 strh \rd, [\r [all...] |
H A D | samsung.S | 12 .macro fifo_level_s5pv210 rd, rx 13 ldr \rd, [\rx, # S3C2410_UFSTAT] 14 ARM_BE8(rev \rd, \rd) 15 and \rd, \rd, #S5PV210_UFSTAT_TXMASK 18 .macro fifo_full_s5pv210 rd, rx 19 ldr \rd, [\rx, # S3C2410_UFSTAT] 20 ARM_BE8(rev \rd, \rd) [all...] |
H A D | omap2plus.S | 63 .macro senduart,rd,rx 64 orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset 66 strb \rd, [\rx] @ send lower byte of rd 67 orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR) 68 bic \rd, \rd, #(0xff << 24) @ restore original rd 71 .macro busyuart,rd,r [all...] |
H A D | imx.S | 33 .macro senduart,rd,rx 34 ARM_BE8(rev \rd, \rd) 35 str \rd, [\rx, #0x40] @ TXDATA 38 .macro waituartcts,rd,rx 41 .macro waituarttxrdy,rd,rx 44 .macro busyuart,rd,rx 45 1002: ldr \rd, [\rx, #0x98] @ SR2 46 ARM_BE8(rev \rd, \rd) [all...] |
H A D | msm.S | 14 .macro senduart, rd, rx 15 ARM_BE8(rev \rd, \rd ) 17 str \rd, [\rx, #0x70] 20 .macro waituartcts,rd,rx 23 .macro waituarttxrdy, rd, rx 25 ldr \rd, [\rx, #0x08] 26 ARM_BE8(rev \rd, \rd ) 27 tst \rd, # [all...] |
H A D | meson.S | 18 .macro senduart,rd,rx 19 str \rd, [\rx, #MESON_AO_UART_WFIFO] 22 .macro busyuart,rd,rx 23 1002: ldr \rd, [\rx, #MESON_AO_UART_STATUS] 24 tst \rd, #MESON_AO_UART_TX_FIFO_EMPTY 28 .macro waituartcts,rd,rx 31 .macro waituarttxrdy,rd,rx 32 1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS] 33 tst \rd, #MESON_AO_UART_TX_FIFO_FULL
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H A D | icedcc.S | 15 .macro senduart, rd, rx 16 mcr p14, 0, \rd, c0, c5, 0 19 .macro busyuart, rd, rx 26 .macro waituartcts, rd, rx 29 .macro waituarttxrdy, rd, rx 30 mov \rd, #0x2000000 32 subs \rd, \rd, #1 42 .macro senduart, rd, rx 43 mcr p14, 0, \rd, c [all...] |
H A D | clps711x.S | 23 .macro waituartcts,rd,rx 26 .macro waituarttxrdy,rd,rx 29 .macro senduart,rd,rx 30 str \rd, [\rx, #UARTDR] 33 .macro busyuart,rd,rx 34 1001: ldr \rd, [\rx, #SYSFLG] 35 tst \rd, #SYSFLG_UBUSY
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H A D | digicolor.S | 20 .macro senduart,rd,rx 21 strb \rd, [\rx, #UA0_EMI_REC] 24 .macro waituartcts,rd,rx 27 .macro waituarttxrdy,rd,rx 30 .macro busyuart,rd,rx 31 1001: ldrb \rd, [\rx, #UA0_STATUS] 32 tst \rd, #UA0_STATUS_TX_READY
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H A D | dc21285.S | 27 .macro senduart,rd,rx 28 str \rd, [\rx, #0x160] @ UARTDR 31 .macro busyuart,rd,rx 32 1001: ldr \rd, [\rx, #0x178] @ UARTFLG 33 tst \rd, #1 << 3 37 .macro waituartcts,rd,rx 40 .macro waituarttxrdy,rd,rx
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H A D | bcm63xx.S | 15 .macro senduart, rd, rx 17 strb \rd, [\rx, #UART_FIFO_REG] 20 .macro waituarttxrdy, rd, rx 21 1001: ldr \rd, [\rx, #UART_IR_REG] 22 tst \rd, #(1 << UART_IR_TXEMPTY) 26 .macro waituartcts, rd, rx 29 .macro busyuart, rd, rx 30 1002: ldr \rd, [\rx, #UART_IR_REG] 31 tst \rd, #(1 << UART_IR_TXTRESH)
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H A D | at91.S | 18 .macro senduart,rd,rx 19 strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register 22 .macro waituarttxrdy,rd,rx 23 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register 24 tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit 28 .macro waituartcts,rd,rx 31 .macro busyuart,rd,rx 32 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register 33 tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
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H A D | 8250.S | 15 .macro store, rd, rx:vararg 16 ARM_BE8(rev \rd, \rd) 17 str \rd, \rx 18 ARM_BE8(rev \rd, \rd) 21 .macro load, rd, rx:vararg 22 ldr \rd, \rx 23 ARM_BE8(rev \rd, \rd) [all...] |
H A D | asm9260.S | 14 .macro waituarttxrdy,rd,rx 17 .macro waituartcts,rd,rx 20 .macro senduart,rd,rx 21 str \rd, [\rx, #0x50] @ TXDATA 24 .macro busyuart,rd,rx 25 1002: ldr \rd, [\rx, #0x60] @ STAT 26 tst \rd, #1 << 27 @ TXEMPTY
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/linux-master/arch/mips/kernel/ |
H A D | branch.c | 436 regs->regs[insn.r_format.rd] = epc + 8;
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