Searched refs:is (Results 251 - 275 of 344) sorted by relevance

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/linux-master/arch/arm/boot/compressed/
H A Dhead-sharpsl.S31 ldrh r3, [r1, #8] @ Load TC6393XB Revison: This is 0x0003
/linux-master/drivers/isdn/hardware/mISDN/
H A Disar.h17 struct isar_hw *is; member in struct:isar_ch
/linux-master/scripts/
H A Dparse-maintainers.pl37 Preferred ordering of section output is:
/linux-master/arch/mips/dec/
H A Dint-handler.S40 * says: a lot of complication here is taken away because:
44 * register is _NOT_ the answer, the common case is one
170 # irq_nr < 0: it is an address
226 # irq_nr < 0: it is an address
/linux-master/arch/x86/crypto/
H A Dcrct10dif-pcl-asm_64.S12 # This software is available to you under a choice of one of two
105 # Load the first 128 data bytes. Byte swapping is necessary to make the
215 pblendvb %xmm2, %xmm1 #xmm0 is implicit
256 # Final CRC value (x^16 * M(x)) mod G(x) is in low 16 bits of xmm0.
326 # is the index vector to shift left by 'len' bytes, and is also {0x80, ...,
H A Dsha256-ssse3-asm.S11 # This software is available to you under a choice of one of two
41 # This code is described in an Intel White-Paper:
316 ## input is [rsp + _XFER + %1 * 4]
354 ## (struct sha256_state is assumed to begin with u32 state[8])
H A Dsha512-avx-asm.S12 # This software is available to you under a choice of one of two
42 # This code is described in an Intel White-Paper:
118 # shld is faster than ror on Sandybridge
275 # "blocks" is the message length in SHA512 blocks
H A Dsha512-ssse3-asm.S12 # This software is available to you under a choice of one of two
42 # This code is described in an Intel White-Paper:
271 # (struct sha512_state is assumed to begin with u64 state[8])
276 # "blocks" is the message length in SHA512 blocks.
/linux-master/arch/arm/mm/
H A Dproc-v7m.S8 * This is the "shell" of the ARMv7-M processor support.
55 * There is no MMU, so here is nothing to do.
156 @ Note the STKALIGN bit is either RW or RAO.
H A Dproc-feroceon.S20 * This is the maximum size of an area which will be invalidated
253 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
299 subne r1, r1, #1 @ top address is inclusive
331 subne r1, r1, #1 @ top address is inclusive
362 subne r1, r1, #1 @ top address is inclusive
471 * lr to do so. The only way without touching main memory is to
472 * use r2 which is normally used to test the VM_EXEC flag, and
473 * compensate locally for the skipped ops if it is not set.
/linux-master/arch/alpha/lib/
H A Dmemchr.S2 This file is part of the GNU C Library.
5 The GNU C Library is free software; you can redistribute it and/or
10 The GNU C Library is distributed in the hope that it will be useful,
32 - the third argument is an unsigned long
48 # the length is the easiest way to avoid trouble.
H A Dstxncpy.S9 * This is an internal routine used by strncpy, stpncpy, and strncat.
39 /* There is a problem with either gdb (as of 4.16) or gas (as of 2.7) that
79 the end-of-count bit is set in t8 iff it applies.
156 t6 == bytemask that is -1 in dest word bytes */
193 the loop is structured to detect zeros in aligned source words.
233 cmpbge zero, t0, t8 # e0 : is the null in this first bit?
299 with 0xff indicating that the destination byte is sacrosanct. */
309 /* If source misalignment is larger than dest misalignment, we need
318 cmpbge zero, t1, t8 # .. e1 : is there a zero?
H A Dev6-stxncpy.S9 * This is an internal routine used by strncpy, stpncpy, and strncat.
49 /* There is a problem with either gdb (as of 4.16) or gas (as of 2.7) that
106 the end-of-count bit is set in t8 iff it applies.
195 t6 == bytemask that is -1 in dest word bytes */
235 the loop is structured to detect zeros in aligned source words.
277 cmpbge zero, t0, t8 # E : is the null in this first bit? (stall)
343 with 0xff indicating that the destination byte is sacrosanct. */
356 /* If source misalignment is larger than dest misalignment, we need
365 cmpbge zero, t1, t8 # E : is there a zero?
/linux-master/arch/parisc/kernel/
H A Dsmp.c61 /* track which CPU is booting */
90 #error verify IRQ_OFFSET(IPI_IRQ) is ipi_interrupt() in new IRQ region
171 smp_debug(100, KERN_DEBUG "CPU%d is alive!\n", this_cpu);
374 ** is executed after receiving the rendezvous signal (an interrupt to
375 ** EIR{0}). MEM_RENDEZ is valid only when it is nonzero and the
395 printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid);
407 pr_info("SMP: bootstrap CPU ID is 0\n");
464 pr_info("CPU %d is now promoted to time-keeper master\n", time_keeper_id);
490 * called on the thread which is askin
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/linux-master/tools/testing/selftests/amd-pstate/
H A Drun.sh41 # Kselftest framework requirement - SKIP code is 4.
129 printf "No cpu is managed by cpufreq core, exiting\n"
247 echo "$0 # Current cpu vendor is $VENDOR."
256 echo "$0 # Current cpufreq scaling driver is $scaling_driver."
264 echo "$0 # Current cpufreq scaling driver is $scaling_driver."
271 echo "$0 # Current comparative test is for $FUNC."
301 echo $msg sysfs is not mounted >&2
326 echo "No cpu is managed by cpufreq core, exiting"
/linux-master/scripts/package/
H A Dmkdebian87 # Create debian/source/ if it is a source package build
228 This is useful for people who need to build external modules
/linux-master/tools/testing/selftests/kvm/x86_64/
H A Damx_test.c25 # error This test is 64-bit only
166 * After XSAVEC, XTILEDATA is cleared in the xstate_bv but is set in
178 * XTILEDATA is cleared in xstate_bv but set in xcomp_bv, this property
179 * remains the same even when amx tiledata is disabled by IA32_XFD.
199 /* Check if #NM is triggered by XFEATURE_MASK_XTILE_DATA */
243 "KVM should enumerate max XSAVE size when XSAVE is supported");
/linux-master/tools/testing/selftests/netfilter/
H A Dbridge_netfilter.sh8 # setup is: ns1 <->,ns0 <-> ns3
11 # Kselftest framework requirement - SKIP code is 4.
112 # veth4 is not a bridge port, only the macvlan on top of it.
129 # the cloned skb is passed up the stack.
148 # ns4 is placed in same subnet as well, but its not
149 # part of the bridge: the corresponding veth4 is not
173 # This should deliver broadcast to macvlan0, which is on top of ns0:br0.
184 echo ERROR: kernel is tainted
/linux-master/arch/x86/entry/vsyscall/
H A Dvsyscall_64.c5 * Based on the original implementation which is:
13 * addresses. This concept is problematic:
16 * - It's awkward to write code that lives in kernel addresses but is
18 * - The whole concept is impossible for 32-bit compat userspace.
21 * As of mid-2014, I believe that there is no new userspace code that
22 * will use a vsyscall if the vDSO is present. I hope that there will
51 #error VSYSCALL config is broken
147 * No point in checking CS -- the only way to get here is a user mode
180 * NULL is a valid user pointer (in the access_ok sense) on 32-bit and
340 * context. It is les
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/linux-master/arch/x86/realmode/rm/
H A Dtrampoline_64.S12 * is a mystery.
14 * On entry to trampoline_start, the processor is in real mode
16 * and IP is zero. Thus, data addresses need to be absolute
82 * operand size is 16bit. Use lgdtl instead to force operand size
87 lgdtl tr_gdt # load gdt with whatever is appropriate
135 * Check for memory encryption support. This is a safety net in
137 * the MSR for this AP. If SME is active and we've gotten this far
138 * then it is safe for us to set the MSR bit and continue. If we
150 * Memory encryption is enabled but the SME enable bit for this
151 * CPU has has not been set. It is saf
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/linux-master/drivers/s390/cio/
H A Dscm.c212 scmdev_setup(scmdev, sale, scm_info->is, scm_info->mbc);
H A Dchsc.h197 u16 is; member in struct:chsc_scm_info
/linux-master/arch/mips/kernel/
H A Dscall32-o32.S2 * This file is subject to the terms and conditions of the GNU General Public
51 bltz t4, bad_stack # -> sp is bad
81 * syscall number is in v0 unless we called syscall(__NR_###)
82 * where the real syscall number is in a0
213 * these hooks for the 32-bit kernel - there is no MIPS64 MT processor
/linux-master/drivers/soc/fsl/qbman/
H A Dqman.c305 #define QM_MCR_RESULT_ERR_NOTEMPTY 0xf3 /* OOS fails if FQ is !empty */
352 * is setup-only, so isn't a cause for a concern. In other words, don't
680 * If PAMU is not available we need to invalidate the cache.
681 * When PAMU is available the cache is updated by stash
862 * The expected valid bit polarity for the next CR command is 0
863 * if RR1 contains a valid response, and is 1 if RR0 contains a
866 * expected valid bit polarity is 1)
927 * its command is submitted and completed. This includes the valid-bit,
989 /* 2-element array. cgrs[0] is mas
1169 u32 is = qm_in(&p->p, QM_REG_ISR) & p->irq_sources; local
1547 __poll_portal_slow(struct qman_portal *p, u32 is) argument
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/linux-master/arch/xtensa/kernel/
H A Dentry.S4 * This file is subject to the terms and conditions of the GNU General Public
149 /* Rotate ws so that the current windowbase is at bit0. */
196 * Assume a2 is: 001001000110001
203 and a3, a3, a2 # max. only one bit is set
298 /* Rotate ws so that the current windowbase is at bit0. */
343 * This is the common exception handler.
375 /* It is now save to restore the EXC_TABLE_FIXUP variable. */
383 /* All unrecoverable states are saved on stack, now, and a1 is valid.
385 * PS.INTLEVEL is set to LOCKLEVEL disabling furhter interrupts,
397 * and is alread
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