/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
H A D | ramnv50.c | 34 #include <subdev/bios/timing.h> 73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) argument 98 timing[6] = (0x2d + T(CL) - T(CWL) + 104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | 109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); 110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | 114 timing[2] = (T(CWL) - 1) << 24 | 118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | 122 timing[4] = (cur4 & 0xffff0000) | 125 timing[ 151 nv50_ram_timing_read(struct nv50_ram *ram, u32 *timing) argument 232 u32 timing[9]; local [all...] |
H A D | gddr3.c | 85 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; 86 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; 87 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
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H A D | sddr3.c | 79 /* XXX: NV50: Get CWL from the timing register */ 88 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; 89 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; 90 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
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/linux-master/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | dml2_mall_phantom.c | 70 mall_alloc_height_blk_aligned = (pipe->stream->timing.v_addressable - 1 + mblk_height - 1) / 246 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + 247 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) 248 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); 266 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / 267 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000; 377 microschedule_lines = (phantom->timing [all...] |
/linux-master/drivers/video/fbdev/via/ |
H A D | via_modesetting.h | 37 void via_set_primary_timing(const struct via_display_timing *timing); 38 void via_set_secondary_timing(const struct via_display_timing *timing);
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/linux-master/drivers/gpu/drm/sti/ |
H A D | sti_awg_utils.h | 33 struct awg_timing *timing);
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/linux-master/include/linux/ |
H A D | leds-expresswire.h | 28 struct expresswire_timing timing; member in struct:expresswire_common_props
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
H A D | dce110_clk_mgr.c | 101 uint32_t vertical_total_min = stream->timing.v_total; 106 vertical_blank_in_pixels = stream->timing.h_total * 108 - stream->timing.v_addressable); 110 * 10000 / stream->timing.pix_clk_100hz; 163 cfg->v_refresh = stream->timing.pix_clk_100hz * 100; 164 cfg->v_refresh /= stream->timing.h_total; 165 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) 166 / stream->timing.v_total; 237 const struct dc_crtc_timing *timing = local 238 &context->streams[0]->timing; [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
H A D | dcn314_fpu.c | 278 * micro_sec_to_vert_lines () - converts time to number of vertical lines for a given timing 284 static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing) argument 288 (((float)timing->h_total * 1000.0) / 289 ((float)timing->pix_clk_100hz / 10.0)); 296 static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing) argument 300 v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom; 301 v_blank = timing->v_total - v_active; 302 v_back_porch = v_blank - timing 322 struct dc_crtc_timing *timing; local [all...] |
/linux-master/drivers/ata/ |
H A D | pata_cs5530.c | 56 /* Now load the right timing register */ 64 * cs5530_set_dmamode - DMA timing setup 76 u32 tuning, timing = 0; local 84 timing = 0x00921250;break; 86 timing = 0x00911140;break; 88 timing = 0x00911030;break; 90 timing = 0x00077771;break; 92 timing = 0x00012121;break; 94 timing = 0x00002020;break; 99 timing | [all...] |
H A D | pata_cmd640.c | 54 struct cmd640_reg *timing = ap->private_data; local 68 /* The second channel has shared timings and the setup timing is 100 /* Load setup timing */ 116 timing->reg58[adev->devno] = (t.active << 4) | t.recover; 134 struct cmd640_reg *timing = ap->private_data; local 136 if (ap->port_no != 0 && adev->devno != timing->last) { 137 pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]); 138 timing->last = adev->devno; 154 struct cmd640_reg *timing; local 156 timing [all...] |
H A D | pata_sis.c | 314 t1 &= 0xC0C00FFF; /* Mask out timing */ 341 u16 timing; local 346 pci_read_config_word(pdev, drive_pci, &timing); 349 /* bits 3-0 hold recovery timing bits 8-10 active timing and 351 timing &= ~0x870F; 352 timing |= mwdma_bits[speed]; 356 timing &= ~0x6000; 357 timing |= udma_bits[speed]; 359 pci_write_config_word(pdev, drive_pci, timing); 380 u16 timing; local 419 u8 timing; local 453 u8 timing; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dce120/ |
H A D | dce120_timing_generator.c | 100 /* determine if given timing can be supported by TG */ 103 const struct dc_crtc_timing *timing, 106 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; 108 (timing->v_total - timing->v_addressable - 109 timing->v_border_top - timing->v_border_bottom) * 115 timing, 121 timing->h_sync_width < tg110->min_h_sync_width || 122 timing 101 dce120_timing_generator_validate_timing( struct timing_generator *tg, const struct dc_crtc_timing *timing, enum signal_type signal) argument 128 dce120_tg_validate_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing) argument 428 dce120_timing_generator_program_blanking( struct timing_generator *tg, const struct dc_crtc_timing *timing) argument 621 dce120_timing_generator_enable_advanced_request( struct timing_generator *tg, bool enable, const struct dc_crtc_timing *timing) argument 694 dce120_tg_program_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing, int vready_offset, int vstartup_start, int vupdate_offset, int vupdate_width, const enum signal_type signal, bool use_vbios) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
H A D | dcn32_resource_helpers.c | 233 if (pipe->stream->timing.v_addressable != pipe->stream->dst.height || 234 pipe->stream->timing.v_addressable != pipe->stream->src.height) { 240 if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height && 241 pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) { 281 if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) { 294 if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) { 435 * Scaling factor for v_blank stretch calculations considering timing in 446 struct dc_crtc_timing *timing local 500 struct dc_crtc_timing *timing = NULL; local [all...] |
/linux-master/drivers/pcmcia/ |
H A D | sa11xx_base.c | 81 struct soc_pcmcia_timing timing; local 86 soc_common_pcmcia_get_timing(skt, &timing); 88 bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io); 89 bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem); 90 bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr); 146 struct soc_pcmcia_timing timing; local 151 soc_common_pcmcia_get_timing(skt, &timing); 153 p+=sprintf(p, "I/O : %uns (%uns)\n", timing.io, 156 p+=sprintf(p, "attribute: %uns (%uns)\n", timing.attr, 159 p+=sprintf(p, "common : %uns (%uns)\n", timing [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dce80/ |
H A D | dce80_timing_generator.c | 109 const struct dc_crtc_timing *timing, 118 program_pix_dur(tg, timing->pix_clk_100hz); 120 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios); 126 const struct dc_crtc_timing *timing) 146 if ((timing->v_sync_width + timing->v_front_porch) <= 3) { 108 program_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing, int vready_offset, int vstartup_start, int vupdate_offset, int vupdate_width, const enum signal_type signal, bool use_vbios) argument 123 dce80_timing_generator_enable_advanced_request( struct timing_generator *tg, bool enable, const struct dc_crtc_timing *timing) argument
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/linux-master/drivers/gpu/drm/amd/display/modules/info_packet/ |
H A D | info_packet.c | 144 if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE) { 250 switch (stream->timing.timing_3d_format) { 343 switch (stream->timing.pixel_encoding) { 362 switch (stream->timing.pixel_encoding) { 401 switch (stream->timing.display_color_depth) { 430 info_packet->sb[17] |= 0x80; /* DB17 bit 7 set to 1 for CEA timing. */ 461 format = stream->timing.timing_3d_format; 465 if (stream->timing.hdmi_vic != 0 466 && stream->timing.h_total >= 3840 467 && stream->timing [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/link/ |
H A D | link_hwss_hpo_frl.c | 42 &stream->timing,
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/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
H A D | dcn10_optc.c | 50 * @timing: Timing parameters used to configure DCN blocks. 52 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) argument 54 if (timing->flags.INTERLACE == 1) { 55 if (timing->v_front_porch < 2) 56 timing->v_front_porch = 2; 58 if (timing->v_front_porch < 1) 59 timing->v_front_porch = 1; 138 * optc1_program_timing() - used by mode timing set Program 184 /* Load horizontal timing */ 334 * vertical timing informatio 585 optc1_validate_timing( struct timing_generator *optc, const struct dc_crtc_timing *timing) argument 1244 optc1_enable_stereo(struct timing_generator *optc, const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) argument 1276 optc1_program_stereo(struct timing_generator *optc, const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) argument 1613 optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
H A D | dcn10_opp.c | 319 const struct dc_crtc_timing *timing) 323 uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right; 324 uint32_t space1_size = timing->v_total - timing->v_addressable; 326 uint32_t space2_size = timing->v_total - timing->v_addressable; 344 if (timing->timing_3d_format == TIMING_3D_FORMAT_FRAME_ALTERNATE) 316 opp1_program_stereo( struct output_pixel_processor *opp, bool enable, const struct dc_crtc_timing *timing) argument
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/linux-master/drivers/gpu/drm/amd/display/modules/freesync/ |
H A D | freesync.c | 118 * 10000) * stream->timing.h_total, 119 stream->timing.pix_clk_100hz)); 136 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), 137 stream->timing.h_total), 1000000); 140 if (v_total < stream->timing.v_total) { 141 ASSERT(v_total < stream->timing.v_total); 142 v_total = stream->timing.v_total; 164 h_total_up_scaled = stream->timing.h_total * 10000; 166 * stream->timing.pix_clk_100hz + (h_total_up_scaled - 1), 170 duration_in_us) * (stream->timing [all...] |
/linux-master/drivers/memory/tegra/ |
H A D | tegra30-emc.c | 409 dev_err(emc->dev, "failed to update timing: %d\n", err); 440 struct emc_timing *timing = NULL; local 445 timing = &emc->timings[i]; 450 if (!timing) { 451 dev_err(emc->dev, "no timing for rate %lu\n", rate); 455 return timing; 458 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing, argument 464 if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) { 475 if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) { 486 if (timing 525 struct emc_timing *timing = emc_find_timing(emc, rate); local 795 struct emc_timing *timing = emc_find_timing(emc, rate); local 888 load_one_timing_from_dt(struct tegra_emc *emc, struct emc_timing *timing, struct device_node *node) argument 983 struct emc_timing *timing; local 1198 struct emc_timing *timing = NULL; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
H A D | dcn314_hwseq.c | 89 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 90 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 91 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 92 dsc_cfg.color_depth = stream->timing.display_color_depth; 94 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 170 &pipe_ctx->stream->timing); [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
H A D | dcn35_fpu.c | 406 * micro_sec_to_vert_lines () - converts time to number of vertical lines for a given timing 412 static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing) argument 416 (((float)timing->h_total * 1000.0) / 417 ((float)timing->pix_clk_100hz / 10.0)); 424 static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing) argument 428 v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom; 429 v_blank = timing->v_total - v_active; 430 v_back_porch = v_blank - timing 450 struct dc_crtc_timing *timing; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
H A D | dcn351_fpu.c | 441 * micro_sec_to_vert_lines () - converts time to number of vertical lines for a given timing 447 static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing) argument 451 (((float)timing->h_total * 1000.0) / 452 ((float)timing->pix_clk_100hz / 10.0)); 459 static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing) argument 463 v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom; 464 v_blank = timing->v_total - v_active; 465 v_back_porch = v_blank - timing 485 struct dc_crtc_timing *timing; local [all...] |