1116743Ssam// SPDX-License-Identifier: GPL-2.0-only 2139530Ssam/* 3116743Ssam * pata_sis.c - SiS ATA driver 4116743Ssam * 5116743Ssam * (C) 2005 Red Hat 6116743Ssam * (C) 2007,2009 Bartlomiej Zolnierkiewicz 7116743Ssam * 8116743Ssam * Based upon linux/drivers/ide/pci/sis5513.c 9116743Ssam * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 10116743Ssam * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer 11116743Ssam * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> 12116743Ssam * SiS Taiwan : for direct support and hardware. 13116743Ssam * Daniela Engert : for initial ATA100 advices and numerous others. 14116743Ssam * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : 15116743Ssam * for checking code correctness, providing patches. 16116743Ssam * Original tests and design on the SiS620 chipset. 17116743Ssam * ATA100 tests and design on the SiS735 chipset. 18116743Ssam * ATA16/33 support from specs 19116743Ssam * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> 20116743Ssam * 21116743Ssam * 22116743Ssam * TODO 23116743Ssam * Check MWDMA on drives that don't support MWDMA speed pio cycles ? 24116743Ssam * More Testing 25116743Ssam */ 26116743Ssam 27116743Ssam#include <linux/kernel.h> 28116743Ssam#include <linux/module.h> 29116743Ssam#include <linux/pci.h> 30116743Ssam#include <linux/blkdev.h> 31116743Ssam#include <linux/delay.h> 32116743Ssam#include <linux/device.h> 33116743Ssam#include <scsi/scsi_host.h> 34116743Ssam#include <linux/libata.h> 35116743Ssam#include <linux/ata.h> 36116743Ssam#include "sis.h" 37116743Ssam 38116743Ssam#define DRV_NAME "pata_sis" 39116743Ssam#define DRV_VERSION "0.5.2" 40116743Ssam 41116743Ssamstruct sis_chipset { 42116743Ssam u16 device; /* PCI host ID */ 43116743Ssam const struct ata_port_info *info; /* Info block */ 44116743Ssam /* Probably add family, cable detect type etc here to clean 45116743Ssam up code later */ 46116743Ssam}; 47116743Ssam 48119783Ssamstruct sis_laptop { 49116743Ssam u16 device; 50138570Ssam u16 subvendor; 51116743Ssam u16 subdevice; 52116743Ssam}; 53116743Ssam 54155481Ssamstatic const struct sis_laptop sis_laptop[] = { 55116743Ssam /* devid, subvendor, subdev */ 56155481Ssam { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ 57155481Ssam { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ 58140438Ssam { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ 59155481Ssam /* end marker */ 60140438Ssam { 0, } 61138570Ssam}; 62155480Ssam 63138570Ssamstatic int sis_short_ata40(struct pci_dev *dev) 64116743Ssam{ 65147067Ssam const struct sis_laptop *lap = &sis_laptop[0]; 66147067Ssam 67147067Ssam while (lap->device) { 68147067Ssam if (lap->device == dev->device && 69147057Ssam lap->subvendor == dev->subsystem_vendor && 70147057Ssam lap->subdevice == dev->subsystem_device) 71147057Ssam return 1; 72147057Ssam lap++; 73147057Ssam } 74147057Ssam 75147057Ssam return 0; 76147057Ssam} 77147057Ssam 78147057Ssam/** 79147057Ssam * sis_old_port_base - return PCI configuration base for dev 80138570Ssam * @adev: device 81116743Ssam * 82119150Ssam * Returns the base of the PCI configuration registers for this port 83138570Ssam * number. 84138570Ssam */ 85116743Ssam 86138570Ssamstatic int sis_old_port_base(struct ata_device *adev) 87138570Ssam{ 88116743Ssam return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); 89138570Ssam} 90138570Ssam 91138570Ssam/** 92138570Ssam * sis_port_base - return PCI configuration base for dev 93138570Ssam * @adev: device 94138570Ssam * 95138570Ssam * Returns the base of the PCI configuration registers for this port 96138570Ssam * number. 97138570Ssam */ 98138570Ssam 99138570Ssamstatic int sis_port_base(struct ata_device *adev) 100116743Ssam{ 101138570Ssam struct ata_port *ap = adev->link->ap; 102116743Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 103147803Ssam int port = 0x40; 104116743Ssam u32 reg54; 105116743Ssam 106138570Ssam /* If bit 30 is set then the registers are mapped at 0x70 not 0x40 */ 107116743Ssam pci_read_config_dword(pdev, 0x54, ®54); 108116743Ssam if (reg54 & 0x40000000) 109116743Ssam port = 0x70; 110140438Ssam 111116743Ssam return port + (8 * ap->port_no) + (4 * adev->devno); 112116743Ssam} 113138570Ssam 114116743Ssam/** 115138570Ssam * sis_133_cable_detect - check for 40/80 pin 116138570Ssam * @ap: Port 117138570Ssam * 118138570Ssam * Perform cable detection for the later UDMA133 capable 119138570Ssam * SiS chipset. 120138570Ssam */ 121138570Ssam 122138570Ssamstatic int sis_133_cable_detect(struct ata_port *ap) 123138570Ssam{ 124138570Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 125138570Ssam u16 tmp; 126138570Ssam 127138570Ssam /* The top bit of this register is the cable detect bit */ 128138570Ssam pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); 129138570Ssam if ((tmp & 0x8000) && !sis_short_ata40(pdev)) 130138570Ssam return ATA_CBL_PATA40; 131138570Ssam return ATA_CBL_PATA80; 132138570Ssam} 133138570Ssam 134138570Ssam/** 135138570Ssam * sis_66_cable_detect - check for 40/80 pin 136138570Ssam * @ap: Port 137138570Ssam * 138138570Ssam * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 139138570Ssam * SiS IDE controllers. 140138570Ssam */ 141138570Ssam 142138570Ssamstatic int sis_66_cable_detect(struct ata_port *ap) 143138570Ssam{ 144138570Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 145155482Ssam u8 tmp; 146138570Ssam 147138570Ssam /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ 148155482Ssam pci_read_config_byte(pdev, 0x48, &tmp); 149155482Ssam tmp >>= ap->port_no; 150155482Ssam if ((tmp & 0x10) && !sis_short_ata40(pdev)) 151155482Ssam return ATA_CBL_PATA40; 152155482Ssam return ATA_CBL_PATA80; 153138570Ssam} 154138570Ssam 155138570Ssam 156138570Ssam/** 157138570Ssam * sis_pre_reset - probe begin 158138570Ssam * @link: ATA link 159138570Ssam * @deadline: deadline jiffies for the operation 160138570Ssam * 161138570Ssam * Set up cable type and use generic probe init 162138570Ssam */ 163138570Ssam 164138570Ssamstatic int sis_pre_reset(struct ata_link *link, unsigned long deadline) 165138570Ssam{ 166138570Ssam static const struct pci_bits sis_enable_bits[] = { 167155486Ssam { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 168155486Ssam { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 169116743Ssam }; 170147256Sbrooks 171138570Ssam struct ata_port *ap = link->ap; 172116743Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 173138570Ssam 174138570Ssam if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) 175138570Ssam return -ENOENT; 176138570Ssam 177138570Ssam /* Clear the FIFO settings. We can't enable the FIFO until 178138570Ssam we know we are poking at a disk */ 179117812Ssam pci_write_config_byte(pdev, 0x4B, 0); 180117812Ssam return ata_sff_prereset(link, deadline); 181138570Ssam} 182116743Ssam 183116743Ssam 184116743Ssam/** 185116743Ssam * sis_set_fifo - Set RWP fifo bits for this device 186116743Ssam * @ap: Port 187116743Ssam * @adev: Device 188138570Ssam * 189155486Ssam * SIS chipsets implement prefetch/postwrite bits for each device 190138570Ssam * on both channels. This functionality is not ATAPI compatible and 191147057Ssam * must be configured according to the class of device present 192138570Ssam */ 193138570Ssam 194138570Ssamstatic void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) 195138570Ssam{ 196138570Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 197138570Ssam u8 fifoctrl; 198140432Ssam u8 mask = 0x11; 199144961Ssam 200147057Ssam mask <<= (2 * ap->port_no); 201147057Ssam mask <<= adev->devno; 202116743Ssam 203116743Ssam /* This holds various bits including the FIFO control */ 204116743Ssam pci_read_config_byte(pdev, 0x4B, &fifoctrl); 205116743Ssam fifoctrl &= ~mask; 206138570Ssam 207138570Ssam /* Enable for ATA (disk) only */ 208116743Ssam if (adev->class == ATA_DEV_ATA) 209140432Ssam fifoctrl |= mask; 210140432Ssam pci_write_config_byte(pdev, 0x4B, fifoctrl); 211140761Ssam} 212140761Ssam 213140432Ssam/** 214140432Ssam * sis_old_set_piomode - Initialize host controller PATA PIO timings 215140432Ssam * @ap: Port whose timings we are configuring 216155477Ssam * @adev: Device we are configuring for. 217155483Ssam * 218138570Ssam * Set PIO mode for device, in host controller PCI config space. This 219155483Ssam * function handles PIO set up for all chips that are pre ATA100 and 220138570Ssam * also early ATA100 devices. 221116743Ssam * 222138570Ssam * LOCKING: 223147057Ssam * None (inherited from caller). 224116743Ssam */ 225140432Ssam 226140432Ssamstatic void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) 227140432Ssam{ 228140432Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 229140432Ssam int port = sis_old_port_base(adev); 230140432Ssam u8 t1, t2; 231140432Ssam int speed = adev->pio_mode - XFER_PIO_0; 232140432Ssam 233138570Ssam static const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; 234119783Ssam static const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; 235119783Ssam 236119783Ssam sis_set_fifo(ap, adev); 237119783Ssam 238119783Ssam pci_read_config_byte(pdev, port, &t1); 239127698Ssam pci_read_config_byte(pdev, port + 1, &t2); 240119783Ssam 241140761Ssam t1 &= ~0x0F; /* Clear active/recovery timings */ 242119783Ssam t2 &= ~0x07; 243119783Ssam 244140761Ssam t1 |= active[speed]; 245154140Ssam t2 |= recovery[speed]; 246119783Ssam 247116743Ssam pci_write_config_byte(pdev, port, t1); 248116743Ssam pci_write_config_byte(pdev, port + 1, t2); 249138570Ssam} 250138570Ssam 251116743Ssam/** 252116743Ssam * sis_100_set_piomode - Initialize host controller PATA PIO timings 253138570Ssam * @ap: Port whose timings we are configuring 254138570Ssam * @adev: Device we are configuring for. 255138570Ssam * 256116743Ssam * Set PIO mode for device, in host controller PCI config space. This 257138570Ssam * function handles PIO set up for ATA100 devices and early ATA133. 258138570Ssam * 259138570Ssam * LOCKING: 260155482Ssam * None (inherited from caller). 261116743Ssam */ 262138570Ssam 263138570Ssamstatic void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) 264138570Ssam{ 265138570Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 266116743Ssam int port = sis_old_port_base(adev); 267116743Ssam int speed = adev->pio_mode - XFER_PIO_0; 268138570Ssam 269138570Ssam static const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; 270116743Ssam 271138570Ssam sis_set_fifo(ap, adev); 272138570Ssam 273138570Ssam pci_write_config_byte(pdev, port, actrec[speed]); 274138570Ssam} 275116743Ssam 276138570Ssam/** 277138570Ssam * sis_133_set_piomode - Initialize host controller PATA PIO timings 278138570Ssam * @ap: Port whose timings we are configuring 279138570Ssam * @adev: Device we are configuring for. 280138570Ssam * 281138570Ssam * Set PIO mode for device, in host controller PCI config space. This 282116743Ssam * function handles PIO set up for the later ATA133 devices. 283116743Ssam * 284155485Ssam * LOCKING: 285116743Ssam * None (inherited from caller). 286116743Ssam */ 287119783Ssam 288140761Ssamstatic void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) 289116743Ssam{ 290121100Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 291121100Ssam int port; 292121100Ssam u32 t1; 293121100Ssam int speed = adev->pio_mode - XFER_PIO_0; 294121100Ssam 295121100Ssam static const u32 timing133[] = { 296121100Ssam 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 297121100Ssam 0x0C266000, 298138570Ssam 0x04263000, 299138570Ssam 0x0C0A3000, 300155482Ssam 0x05093000 301155482Ssam }; 302155482Ssam static const u32 timing100[] = { 303155482Ssam 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 304155482Ssam 0x091C4000, 305121100Ssam 0x031C2000, 306121100Ssam 0x09072000, 307121100Ssam 0x04062000 308121100Ssam }; 309121100Ssam 310121100Ssam sis_set_fifo(ap, adev); 311116743Ssam 312116743Ssam port = sis_port_base(adev); 313116743Ssam pci_read_config_dword(pdev, port, &t1); 314116743Ssam t1 &= 0xC0C00FFF; /* Mask out timing */ 315116743Ssam 316116743Ssam if (t1 & 0x08) /* 100 or 133 ? */ 317116743Ssam t1 |= timing133[speed]; 318116743Ssam else 319116743Ssam t1 |= timing100[speed]; 320116743Ssam pci_write_config_byte(pdev, port, t1); 321138570Ssam} 322138570Ssam 323116743Ssam/** 324116743Ssam * sis_old_set_dmamode - Initialize host controller PATA DMA timings 325116743Ssam * @ap: Port whose timings we are configuring 326116743Ssam * @adev: Device to program 327116743Ssam * 328116743Ssam * Set UDMA/MWDMA mode for device, in host controller PCI config space. 329138570Ssam * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike 330138570Ssam * the old ide/pci driver. 331116743Ssam * 332116743Ssam * LOCKING: 333116743Ssam * None (inherited from caller). 334116743Ssam */ 335116743Ssam 336116743Ssamstatic void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) 337116743Ssam{ 338116743Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 339116743Ssam int speed = adev->dma_mode - XFER_MW_DMA_0; 340116743Ssam int drive_pci = sis_old_port_base(adev); 341116743Ssam u16 timing; 342116743Ssam 343138570Ssam static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 344138570Ssam static const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; 345116743Ssam 346116743Ssam pci_read_config_word(pdev, drive_pci, &timing); 347138570Ssam 348138570Ssam if (adev->dma_mode < XFER_UDMA_0) { 349116743Ssam /* bits 3-0 hold recovery timing bits 8-10 active timing and 350116743Ssam the higher bits are dependent on the device */ 351116743Ssam timing &= ~0x870F; 352116743Ssam timing |= mwdma_bits[speed]; 353116743Ssam } else { 354116743Ssam /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ 355116743Ssam speed = adev->dma_mode - XFER_UDMA_0; 356116743Ssam timing &= ~0x6000; 357116743Ssam timing |= udma_bits[speed]; 358116743Ssam } 359116743Ssam pci_write_config_word(pdev, drive_pci, timing); 360116743Ssam} 361116743Ssam 362116743Ssam/** 363116743Ssam * sis_66_set_dmamode - Initialize host controller PATA DMA timings 364116743Ssam * @ap: Port whose timings we are configuring 365116743Ssam * @adev: Device to program 366116743Ssam * 367116743Ssam * Set UDMA/MWDMA mode for device, in host controller PCI config space. 368116743Ssam * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike 369116743Ssam * the old ide/pci driver. 370116743Ssam * 371116743Ssam * LOCKING: 372116743Ssam * None (inherited from caller). 373116743Ssam */ 374116743Ssam 375138570Ssamstatic void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) 376138570Ssam{ 377116743Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 378116743Ssam int speed = adev->dma_mode - XFER_MW_DMA_0; 379116743Ssam int drive_pci = sis_old_port_base(adev); 380116743Ssam u16 timing; 381116743Ssam 382116743Ssam /* MWDMA 0-2 and UDMA 0-5 */ 383116743Ssam static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 384116743Ssam static const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 }; 385116743Ssam 386116743Ssam pci_read_config_word(pdev, drive_pci, &timing); 387138570Ssam 388138570Ssam if (adev->dma_mode < XFER_UDMA_0) { 389116743Ssam /* bits 3-0 hold recovery timing bits 8-10 active timing and 390116743Ssam the higher bits are dependent on the device, bit 15 udma */ 391138570Ssam timing &= ~0x870F; 392138570Ssam timing |= mwdma_bits[speed]; 393116743Ssam } else { 394138570Ssam /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ 395138570Ssam speed = adev->dma_mode - XFER_UDMA_0; 396138570Ssam timing &= ~0xF000; 397138570Ssam timing |= udma_bits[speed]; 398138570Ssam } 399116743Ssam pci_write_config_word(pdev, drive_pci, timing); 400116743Ssam} 401116743Ssam 402116743Ssam/** 403116743Ssam * sis_100_set_dmamode - Initialize host controller PATA DMA timings 404116743Ssam * @ap: Port whose timings we are configuring 405116743Ssam * @adev: Device to program 406116743Ssam * 407138570Ssam * Set UDMA/MWDMA mode for device, in host controller PCI config space. 408138570Ssam * Handles UDMA66 and early UDMA100 devices. 409138570Ssam * 410116743Ssam * LOCKING: 411116743Ssam * None (inherited from caller). 412116743Ssam */ 413116743Ssam 414116743Ssamstatic void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) 415116743Ssam{ 416138570Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 417138570Ssam int speed = adev->dma_mode - XFER_MW_DMA_0; 418138570Ssam int drive_pci = sis_old_port_base(adev); 419138570Ssam u8 timing; 420116743Ssam 421116743Ssam static const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; 422138570Ssam 423138570Ssam pci_read_config_byte(pdev, drive_pci + 1, &timing); 424138570Ssam 425138570Ssam if (adev->dma_mode < XFER_UDMA_0) { 426138570Ssam /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 427138570Ssam } else { 428138570Ssam /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 429138570Ssam speed = adev->dma_mode - XFER_UDMA_0; 430138570Ssam timing &= ~0x8F; 431138570Ssam timing |= udma_bits[speed]; 432138570Ssam } 433138570Ssam pci_write_config_byte(pdev, drive_pci + 1, timing); 434138570Ssam} 435138570Ssam 436138570Ssam/** 437138570Ssam * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings 438138570Ssam * @ap: Port whose timings we are configuring 439138570Ssam * @adev: Device to program 440138570Ssam * 441138570Ssam * Set UDMA/MWDMA mode for device, in host controller PCI config space. 442138570Ssam * Handles early SiS 961 bridges. 443138570Ssam * 444138570Ssam * LOCKING: 445138570Ssam * None (inherited from caller). 446138570Ssam */ 447138570Ssam 448138570Ssamstatic void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) 449138570Ssam{ 450155489Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 451155489Ssam int speed = adev->dma_mode - XFER_MW_DMA_0; 452138570Ssam int drive_pci = sis_old_port_base(adev); 453138570Ssam u8 timing; 454138570Ssam /* Low 4 bits are timing */ 455138570Ssam static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; 456138570Ssam 457138570Ssam pci_read_config_byte(pdev, drive_pci + 1, &timing); 458138570Ssam 459138570Ssam if (adev->dma_mode < XFER_UDMA_0) { 460138570Ssam /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 461138570Ssam } else { 462138570Ssam /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 463138570Ssam speed = adev->dma_mode - XFER_UDMA_0; 464138570Ssam timing &= ~0x8F; 465138570Ssam timing |= udma_bits[speed]; 466138570Ssam } 467138570Ssam pci_write_config_byte(pdev, drive_pci + 1, timing); 468138570Ssam} 469138570Ssam 470138570Ssam/** 471138570Ssam * sis_133_set_dmamode - Initialize host controller PATA DMA timings 472138570Ssam * @ap: Port whose timings we are configuring 473138570Ssam * @adev: Device to program 474138570Ssam * 475138570Ssam * Set UDMA/MWDMA mode for device, in host controller PCI config space. 476138570Ssam * 477138570Ssam * LOCKING: 478138570Ssam * None (inherited from caller). 479138570Ssam */ 480138570Ssam 481138570Ssamstatic void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) 482138570Ssam{ 483138570Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 484138570Ssam int port; 485138570Ssam u32 t1; 486138570Ssam 487138570Ssam port = sis_port_base(adev); 488138570Ssam pci_read_config_dword(pdev, port, &t1); 489138570Ssam 490138570Ssam if (adev->dma_mode < XFER_UDMA_0) { 491138570Ssam /* Recovery << 24 | Act << 16 | Ini << 12, like PIO modes */ 492147057Ssam static const u32 timing_u100[] = { 0x19154000, 0x06072000, 0x04062000 }; 493147057Ssam static const u32 timing_u133[] = { 0x221C6000, 0x0C0A3000, 0x05093000 }; 494147057Ssam int speed = adev->dma_mode - XFER_MW_DMA_0; 495147057Ssam 496147057Ssam t1 &= 0xC0C00FFF; 497147057Ssam /* disable UDMA */ 498147057Ssam t1 &= ~0x00000004; 499147057Ssam if (t1 & 0x08) 500154140Ssam t1 |= timing_u133[speed]; 501154140Ssam else 502154140Ssam t1 |= timing_u100[speed]; 503154140Ssam } else { 504154140Ssam /* bits 4- cycle time 8 - cvs time */ 505154140Ssam static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; 506154140Ssam static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; 507154140Ssam int speed = adev->dma_mode - XFER_UDMA_0; 508154140Ssam 509116743Ssam t1 &= ~0x00000FF0; 510116743Ssam /* enable UDMA */ 511116743Ssam t1 |= 0x00000004; 512123044Ssam if (t1 & 0x08) 513123044Ssam t1 |= timing_u133[speed]; 514116743Ssam else 515116743Ssam t1 |= timing_u100[speed]; 516116743Ssam } 517116743Ssam pci_write_config_dword(pdev, port, t1); 518116743Ssam} 519116743Ssam 520138570Ssam/** 521116743Ssam * sis_133_mode_filter - mode selection filter 522138570Ssam * @adev: ATA device 523116743Ssam * @mask: received mask to manipulate and pass back 524138570Ssam * 525138570Ssam * Block UDMA6 on devices that do not support it. 526116743Ssam */ 527116743Ssam 528116743Ssamstatic unsigned int sis_133_mode_filter(struct ata_device *adev, unsigned int mask) 529138570Ssam{ 530138570Ssam struct ata_port *ap = adev->link->ap; 531138570Ssam struct pci_dev *pdev = to_pci_dev(ap->host->dev); 532138570Ssam int port = sis_port_base(adev); 533138570Ssam u32 t1; 534116743Ssam 535 pci_read_config_dword(pdev, port, &t1); 536 /* if ATA133 is disabled, mask it out */ 537 if (!(t1 & 0x08)) 538 mask &= ~(0xC0 << ATA_SHIFT_UDMA); 539 return mask; 540} 541 542static const struct scsi_host_template sis_sht = { 543 ATA_BMDMA_SHT(DRV_NAME), 544}; 545 546static struct ata_port_operations sis_133_for_sata_ops = { 547 .inherits = &ata_bmdma_port_ops, 548 .set_piomode = sis_133_set_piomode, 549 .set_dmamode = sis_133_set_dmamode, 550 .cable_detect = sis_133_cable_detect, 551}; 552 553static struct ata_port_operations sis_base_ops = { 554 .inherits = &ata_bmdma_port_ops, 555 .prereset = sis_pre_reset, 556}; 557 558static struct ata_port_operations sis_133_ops = { 559 .inherits = &sis_base_ops, 560 .set_piomode = sis_133_set_piomode, 561 .set_dmamode = sis_133_set_dmamode, 562 .cable_detect = sis_133_cable_detect, 563 .mode_filter = sis_133_mode_filter, 564}; 565 566static struct ata_port_operations sis_133_early_ops = { 567 .inherits = &sis_base_ops, 568 .set_piomode = sis_100_set_piomode, 569 .set_dmamode = sis_133_early_set_dmamode, 570 .cable_detect = sis_66_cable_detect, 571}; 572 573static struct ata_port_operations sis_100_ops = { 574 .inherits = &sis_base_ops, 575 .set_piomode = sis_100_set_piomode, 576 .set_dmamode = sis_100_set_dmamode, 577 .cable_detect = sis_66_cable_detect, 578}; 579 580static struct ata_port_operations sis_66_ops = { 581 .inherits = &sis_base_ops, 582 .set_piomode = sis_old_set_piomode, 583 .set_dmamode = sis_66_set_dmamode, 584 .cable_detect = sis_66_cable_detect, 585}; 586 587static struct ata_port_operations sis_old_ops = { 588 .inherits = &sis_base_ops, 589 .set_piomode = sis_old_set_piomode, 590 .set_dmamode = sis_old_set_dmamode, 591 .cable_detect = ata_cable_40wire, 592}; 593 594static const struct ata_port_info sis_info = { 595 .flags = ATA_FLAG_SLAVE_POSS, 596 .pio_mask = ATA_PIO4, 597 .mwdma_mask = ATA_MWDMA2, 598 /* No UDMA */ 599 .port_ops = &sis_old_ops, 600}; 601static const struct ata_port_info sis_info33 = { 602 .flags = ATA_FLAG_SLAVE_POSS, 603 .pio_mask = ATA_PIO4, 604 .mwdma_mask = ATA_MWDMA2, 605 .udma_mask = ATA_UDMA2, 606 .port_ops = &sis_old_ops, 607}; 608static const struct ata_port_info sis_info66 = { 609 .flags = ATA_FLAG_SLAVE_POSS, 610 .pio_mask = ATA_PIO4, 611 /* No MWDMA */ 612 .udma_mask = ATA_UDMA4, 613 .port_ops = &sis_66_ops, 614}; 615static const struct ata_port_info sis_info100 = { 616 .flags = ATA_FLAG_SLAVE_POSS, 617 .pio_mask = ATA_PIO4, 618 /* No MWDMA */ 619 .udma_mask = ATA_UDMA5, 620 .port_ops = &sis_100_ops, 621}; 622static const struct ata_port_info sis_info100_early = { 623 .flags = ATA_FLAG_SLAVE_POSS, 624 .pio_mask = ATA_PIO4, 625 /* No MWDMA */ 626 .udma_mask = ATA_UDMA5, 627 .port_ops = &sis_66_ops, 628}; 629static const struct ata_port_info sis_info133 = { 630 .flags = ATA_FLAG_SLAVE_POSS, 631 .pio_mask = ATA_PIO4, 632 .mwdma_mask = ATA_MWDMA2, 633 .udma_mask = ATA_UDMA6, 634 .port_ops = &sis_133_ops, 635}; 636const struct ata_port_info sis_info133_for_sata = { 637 .flags = ATA_FLAG_SLAVE_POSS, 638 .pio_mask = ATA_PIO4, 639 /* No MWDMA */ 640 .udma_mask = ATA_UDMA6, 641 .port_ops = &sis_133_for_sata_ops, 642}; 643static const struct ata_port_info sis_info133_early = { 644 .flags = ATA_FLAG_SLAVE_POSS, 645 .pio_mask = ATA_PIO4, 646 /* No MWDMA */ 647 .udma_mask = ATA_UDMA6, 648 .port_ops = &sis_133_early_ops, 649}; 650 651/* Privately shared with the SiS180 SATA driver, not for use elsewhere */ 652EXPORT_SYMBOL_GPL(sis_info133_for_sata); 653 654static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) 655{ 656 u16 regw; 657 u8 reg; 658 659 if (sis->info == &sis_info133) { 660 pci_read_config_word(pdev, 0x50, ®w); 661 if (regw & 0x08) 662 pci_write_config_word(pdev, 0x50, regw & ~0x08); 663 pci_read_config_word(pdev, 0x52, ®w); 664 if (regw & 0x08) 665 pci_write_config_word(pdev, 0x52, regw & ~0x08); 666 return; 667 } 668 669 if (sis->info == &sis_info133_early || sis->info == &sis_info100) { 670 /* Fix up latency */ 671 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 672 /* Set compatibility bit */ 673 pci_read_config_byte(pdev, 0x49, ®); 674 if (!(reg & 0x01)) 675 pci_write_config_byte(pdev, 0x49, reg | 0x01); 676 return; 677 } 678 679 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { 680 /* Fix up latency */ 681 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 682 /* Set compatibility bit */ 683 pci_read_config_byte(pdev, 0x52, ®); 684 if (!(reg & 0x04)) 685 pci_write_config_byte(pdev, 0x52, reg | 0x04); 686 return; 687 } 688 689 if (sis->info == &sis_info33) { 690 pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); 691 if (( reg & 0x0F ) != 0x00) 692 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); 693 /* Fall through to ATA16 fixup below */ 694 } 695 696 if (sis->info == &sis_info || sis->info == &sis_info33) { 697 /* force per drive recovery and active timings 698 needed on ATA_33 and below chips */ 699 pci_read_config_byte(pdev, 0x52, ®); 700 if (!(reg & 0x08)) 701 pci_write_config_byte(pdev, 0x52, reg|0x08); 702 return; 703 } 704 705 BUG(); 706} 707 708/** 709 * sis_init_one - Register SiS ATA PCI device with kernel services 710 * @pdev: PCI device to register 711 * @ent: Entry in sis_pci_tbl matching with @pdev 712 * 713 * Called from kernel PCI layer. We probe for combined mode (sigh), 714 * and then hand over control to libata, for it to do the rest. 715 * 716 * LOCKING: 717 * Inherited from PCI layer (may sleep). 718 * 719 * RETURNS: 720 * Zero on success, or -ERRNO value. 721 */ 722 723static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 724{ 725 const struct ata_port_info *ppi[] = { NULL, NULL }; 726 struct pci_dev *host = NULL; 727 struct sis_chipset *chipset = NULL; 728 struct sis_chipset *sets; 729 int rc; 730 731 static struct sis_chipset sis_chipsets[] = { 732 733 { 0x0968, &sis_info133 }, 734 { 0x0966, &sis_info133 }, 735 { 0x0965, &sis_info133 }, 736 { 0x0745, &sis_info100 }, 737 { 0x0735, &sis_info100 }, 738 { 0x0733, &sis_info100 }, 739 { 0x0635, &sis_info100 }, 740 { 0x0633, &sis_info100 }, 741 742 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ 743 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ 744 745 { 0x0640, &sis_info66 }, 746 { 0x0630, &sis_info66 }, 747 { 0x0620, &sis_info66 }, 748 { 0x0540, &sis_info66 }, 749 { 0x0530, &sis_info66 }, 750 751 { 0x5600, &sis_info33 }, 752 { 0x5598, &sis_info33 }, 753 { 0x5597, &sis_info33 }, 754 { 0x5591, &sis_info33 }, 755 { 0x5582, &sis_info33 }, 756 { 0x5581, &sis_info33 }, 757 758 { 0x5596, &sis_info }, 759 { 0x5571, &sis_info }, 760 { 0x5517, &sis_info }, 761 { 0x5511, &sis_info }, 762 763 {0} 764 }; 765 static struct sis_chipset sis133_early = { 766 0x0, &sis_info133_early 767 }; 768 static struct sis_chipset sis133 = { 769 0x0, &sis_info133 770 }; 771 static struct sis_chipset sis100_early = { 772 0x0, &sis_info100_early 773 }; 774 static struct sis_chipset sis100 = { 775 0x0, &sis_info100 776 }; 777 778 ata_print_version_once(&pdev->dev, DRV_VERSION); 779 780 rc = pcim_enable_device(pdev); 781 if (rc) 782 return rc; 783 784 /* We have to find the bridge first */ 785 for (sets = &sis_chipsets[0]; sets->device; sets++) { 786 host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); 787 if (host != NULL) { 788 chipset = sets; /* Match found */ 789 if (sets->device == 0x630) { /* SIS630 */ 790 if (host->revision >= 0x30) /* 630 ET */ 791 chipset = &sis100_early; 792 } 793 break; 794 } 795 } 796 797 /* Look for concealed bridges */ 798 if (chipset == NULL) { 799 /* Second check */ 800 u32 idemisc; 801 u16 trueid; 802 803 /* Disable ID masking and register remapping then 804 see what the real ID is */ 805 806 pci_read_config_dword(pdev, 0x54, &idemisc); 807 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); 808 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 809 pci_write_config_dword(pdev, 0x54, idemisc); 810 811 switch(trueid) { 812 case 0x5518: /* SIS 962/963 */ 813 dev_info(&pdev->dev, 814 "SiS 962/963 MuTIOL IDE UDMA133 controller\n"); 815 chipset = &sis133; 816 if ((idemisc & 0x40000000) == 0) { 817 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); 818 dev_info(&pdev->dev, 819 "Switching to 5513 register mapping\n"); 820 } 821 break; 822 case 0x0180: /* SIS 965/965L */ 823 chipset = &sis133; 824 break; 825 case 0x1180: /* SIS 966/966L */ 826 chipset = &sis133; 827 break; 828 } 829 } 830 831 /* Further check */ 832 if (chipset == NULL) { 833 struct pci_dev *lpc_bridge; 834 u16 trueid; 835 u8 prefctl; 836 u8 idecfg; 837 838 /* Try the second unmasking technique */ 839 pci_read_config_byte(pdev, 0x4a, &idecfg); 840 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); 841 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 842 pci_write_config_byte(pdev, 0x4a, idecfg); 843 844 switch(trueid) { 845 case 0x5517: 846 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ 847 if (lpc_bridge == NULL) 848 break; 849 pci_read_config_byte(pdev, 0x49, &prefctl); 850 pci_dev_put(lpc_bridge); 851 852 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { 853 chipset = &sis133_early; 854 break; 855 } 856 chipset = &sis100; 857 break; 858 } 859 } 860 pci_dev_put(host); 861 862 /* No chipset info, no support */ 863 if (chipset == NULL) 864 return -ENODEV; 865 866 ppi[0] = chipset->info; 867 868 sis_fixup(pdev, chipset); 869 870 return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0); 871} 872 873#ifdef CONFIG_PM_SLEEP 874static int sis_reinit_one(struct pci_dev *pdev) 875{ 876 struct ata_host *host = pci_get_drvdata(pdev); 877 int rc; 878 879 rc = ata_pci_device_do_resume(pdev); 880 if (rc) 881 return rc; 882 883 sis_fixup(pdev, host->private_data); 884 885 ata_host_resume(host); 886 return 0; 887} 888#endif 889 890static const struct pci_device_id sis_pci_tbl[] = { 891 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ 892 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ 893 { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ 894 895 { } 896}; 897 898static struct pci_driver sis_pci_driver = { 899 .name = DRV_NAME, 900 .id_table = sis_pci_tbl, 901 .probe = sis_init_one, 902 .remove = ata_pci_remove_one, 903#ifdef CONFIG_PM_SLEEP 904 .suspend = ata_pci_device_suspend, 905 .resume = sis_reinit_one, 906#endif 907}; 908 909module_pci_driver(sis_pci_driver); 910 911MODULE_AUTHOR("Alan Cox"); 912MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); 913MODULE_LICENSE("GPL"); 914MODULE_DEVICE_TABLE(pci, sis_pci_tbl); 915MODULE_VERSION(DRV_VERSION); 916