Searched refs:reg1 (Results 26 - 50 of 175) sorted by relevance

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/linux-master/arch/s390/include/asm/
H A Dtimex.h145 unsigned long reg1 = (unsigned long)(ptff_block); \
150 " lgr 1,%[reg1]\n" \
154 : [rc] "=&d" (rc), "+m" (*(struct addrtype *)reg1) \
155 : [reg0] "d" (reg0), [reg1] "d" (reg1) \
/linux-master/drivers/mcb/
H A Dmcb-parse.c47 __le32 reg1; local
54 reg1 = readl(&gdd->reg1);
59 mdev->id = GDD_DEV(reg1);
60 mdev->rev = GDD_REV(reg1);
61 mdev->var = GDD_VAR(reg1);
93 mdev->irq.start = GDD_IRQ(reg1);
94 mdev->irq.end = GDD_IRQ(reg1);
120 /* skip reg1 */
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
210 .enable_reg = SRI(reg1, block, reg_num),\
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
224 .enable_reg = SRI_DMUB(reg1),\
226 reg1 ## __ ## mask1 ## _MASK,\
228 reg1 ## __ ## mask1 ## _MASK,\
229 ~reg1 ## _
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn35/
H A Dirq_service_dcn35.c207 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
208 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
210 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
221 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\
222 REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
224 reg1 ## __ ## mask1 ## _MASK,\
226 reg1 ## __ ## mask1 ## _MASK,\
228 ~reg1 ## _
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
216 .enable_reg = SRI(reg1, block, reg_num),\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
230 .enable_reg = SRI_DMUB(reg1),\
232 reg1 ## __ ## mask1 ## _MASK,\
234 reg1 ## __ ## mask1 ## _MASK,\
235 ~reg1 ## _
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
196 .enable_reg = SRI(reg1, block, reg_num),\
197 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
200 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
214 .enable_reg = SRI_DMUB(reg1),\
216 reg1 ## __ ## mask1 ## _MASK,\
218 reg1 ## __ ## mask1 ## _MASK,\
219 ~reg1 ## _
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
221 .enable_reg = SRI(reg1, block, reg_num),\
223 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
226 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
235 .enable_reg = SRI_DMUB(reg1),\
237 reg1 ## __ ## mask1 ## _MASK,\
239 reg1 ## __ ## mask1 ## _MASK,\
240 ~reg1 ## _
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
209 .enable_reg = SRI(reg1, block, reg_num),\
211 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
223 .enable_reg = SRI_DMUB(reg1),\
225 reg1 ## __ ## mask1 ## _MASK,\
227 reg1 ## __ ## mask1 ## _MASK,\
228 ~reg1 ## _
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
211 .enable_reg = SRI(reg1, block, reg_num),\
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
216 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
225 .enable_reg = SRI_DMUB(reg1),\
227 reg1 ## __ ## mask1 ## _MASK,\
229 reg1 ## __ ## mask1 ## _MASK,\
230 ~reg1 ## _
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c213 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
214 .enable_reg = SRI(reg1, block, reg_num),\
216 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
219 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
227 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
228 .enable_reg = SRI_DMUB(reg1),\
230 reg1 ## __ ## mask1 ## _MASK,\
232 reg1 ## __ ## mask1 ## _MASK,\
233 ~reg1 ## _
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c186 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
187 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
193 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
200 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\
201 REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
203 reg1 ## __ ## mask1 ## _MASK,\
205 reg1 ## __ ## mask1 ## _MASK,\
207 ~reg1 ## _
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/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_pmdemand.c387 u32 reg1, reg2; local
400 reg1 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
406 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1);
408 REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1);
410 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1);
412 REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1);
414 REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1);
416 REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1);
471 u32 *reg1, u32 *reg2, bool serialized)
501 update_reg(reg1, qclk_gv_b
469 intel_pmdemand_update_params(const struct intel_pmdemand_state *new, const struct intel_pmdemand_state *old, u32 *reg1, u32 *reg2, bool serialized) argument
524 u32 reg1, mod_reg1; local
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/linux-master/arch/parisc/net/
H A Dbpf_jit.h103 #define hppa_or(reg1, reg2, target) \
104 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x09, target) /* or reg1,reg2,target */
105 #define hppa_or_cond(reg1, reg2, cond, f, target) \
106 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x09, target)
107 #define hppa_and(reg1, reg2, target) \
108 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x08, target) /* and reg1,reg2,target */
109 #define hppa_and_cond(reg1, reg2, cond, f, target) \
110 hppa_t6_insn(0x02, reg2, reg1, con
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/linux-master/arch/x86/crypto/
H A Dcrct10dif-pcl-asm_64.S64 # Fold reg1, reg2 into the next 32 data bytes, storing the result back into
65 # reg1, reg2.
66 .macro fold_32_bytes offset, reg1, reg2
71 movdqa \reg1, %xmm8
73 pclmulqdq $0x00, FOLD_CONSTS, \reg1
77 pxor %xmm9 , \reg1
78 xorps %xmm8 , \reg1
/linux-master/arch/s390/kvm/
H A Dpriv.c260 int reg1, reg2; local
273 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2);
299 vcpu->run->s.regs.gprs[reg1] &= ~0xff;
300 vcpu->run->s.regs.gprs[reg1] |= key;
307 int reg1, reg2; local
320 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2);
358 int reg1, reg2; local
378 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2);
380 key = vcpu->run->s.regs.gprs[reg1] & 0xfe;
420 /* skey in reg1 i
1015 int reg1, reg2; local
1045 int reg1, reg2; local
1311 int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; local
1350 int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; local
1384 int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; local
1422 int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; local
[all...]
/linux-master/arch/powerpc/include/asm/book3s/32/
H A Dmmu-hash.h71 .macro uus_addi sr reg1 reg2 imm
73 addi \reg1,\reg2,\imm
77 .macro uus_mtsr sr reg1
79 mtsr \sr, \reg1
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c185 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) argument
187 bool head_a = (reg1 == 0x680508);
198 setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1, argument
204 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
205 uint32_t oldpll1 = nvkm_rd32(device, reg1);
212 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
220 if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */
222 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
246 switch (reg1) {
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/linux-master/arch/arm/crypto/
H A Dcrct10dif-ce-core.S115 // Fold reg1, reg2 into the next 32 data bytes, storing the result back
116 // into reg1, reg2.
117 .macro fold_32_bytes, reg1, reg2
120 vmull.p64 q8, \reg1\()h, FOLD_CONST_H
121 vmull.p64 \reg1, \reg1\()l, FOLD_CONST_L
130 veor.8 \reg1, \reg1, q8
132 veor.8 \reg1, \reg1, q1
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/linux-master/arch/s390/boot/
H A Dphysmem_info.c60 unsigned long reg1, reg2, ry; local
71 " epsw %[reg1],%[reg2]\n"
72 " st %[reg1],0(%[psw_pgm])\n"
74 " larl %[reg1],1f\n"
75 " stg %[reg1],8(%[psw_pgm])\n"
80 : [reg1] "=&d" (reg1),
114 unsigned long reg1, reg2; local
120 " epsw %[reg1],%[reg2]\n"
121 " st %[reg1],
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/linux-master/arch/x86/events/intel/
H A Duncore_snbep.c640 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
642 if (reg1->idx != EXTRA_REG_NONE)
643 wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0));
931 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
939 if (reg1->alloc & (0x1 << i))
942 reg1->alloc = 0;
949 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
955 if (reg1->idx == EXTRA_REG_NONE)
960 if (!(reg1->idx & (0x1 << i)))
962 if (!uncore_box_is_fake(box) && (reg1
1016 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
1061 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
1080 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
1121 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
1134 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
1189 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
1206 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
1757 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
1779 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
2185 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
2607 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
2740 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
2763 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
2858 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
3626 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
4638 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
4652 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
4842 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
5299 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
5910 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
5922 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; local
5932 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn201/
H A Dirq_service_dcn201.c152 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
153 .enable_reg = SRI(reg1, block, reg_num),\
155 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
157 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
158 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn303/
H A Dirq_service_dcn303.c138 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
139 .enable_reg = SRI(reg1, block, reg_num),\
140 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
142 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
143 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn10/
H A Dirq_service_dcn10.c200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
201 .enable_reg = SRI(reg1, block, reg_num),\
203 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
205 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
206 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dce120/
H A Dirq_service_dce120.c103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
104 .enable_reg = SRI(reg1, block, reg_num),\
106 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
108 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
109 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn20/
H A Dirq_service_dcn20.c203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
204 .enable_reg = SRI(reg1, block, reg_num),\
206 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
208 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
209 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

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