Searched refs:control_reg (Results 26 - 31 of 31) sorted by relevance

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/linux-master/drivers/clk/ti/
H A Ddpll44xx.c129 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
H A Ddpll.c318 if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))
/linux-master/include/linux/clk/
H A Dti.h35 * @control_reg: register containing the DPLL mode bitfield
36 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
52 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
56 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
57 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
58 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
65 * @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg
67 * @control_reg
93 struct clk_omap_reg control_reg; member in struct:dpll_data
/linux-master/drivers/tty/serial/
H A Dpmac_zilog.c1365 uap->control_reg = uap->port.membase;
1366 uap->data_reg = uap->control_reg + 0x10;
1451 iounmap(uap->control_reg);
1642 uap->control_reg = uap->port.membase;
1643 uap->data_reg = uap->control_reg + 4;
/linux-master/drivers/net/ethernet/ti/
H A Dcpsw.c680 u32 control_reg; local
690 control_reg = readl(&cpsw->regs->control);
691 control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP;
692 writel(control_reg, &cpsw->regs->control);
H A Dcpsw_new.c551 u32 control_reg; local
560 control_reg = readl(&cpsw->regs->control);
561 control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP;
562 writel(control_reg, &cpsw->regs->control);

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