| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 115 #define BASE(seg) BASE_INNER(seg) macro
118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
121 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
127 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
138 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
149 REG_STRUCT[id].reg_name = BASE(re
[all...] |
| /linux-master/arch/sparc/kernel/ |
| H A D | sun4v_tlb_miss.S | 10 /* Load ITLB fault information into VADDR and CTX, using BASE. */
11 #define LOAD_ITLB_INFO(BASE, VADDR, CTX) \
12 ldx [BASE + HV_FAULT_I_ADDR_OFFSET], VADDR; \
13 ldx [BASE + HV_FAULT_I_CTX_OFFSET], CTX;
15 /* Load DTLB fault information into VADDR and CTX, using BASE. */
16 #define LOAD_DTLB_INFO(BASE, VADDR, CTX) \
17 ldx [BASE + HV_FAULT_D_ADDR_OFFSET], VADDR; \
18 ldx [BASE + HV_FAULT_D_CTX_OFFSET], CTX;
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| /linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
| H A D | irq_service_dcn32.c | 198 #define BASE(seg) \ macro
202 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
206 BASE(reg ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn35/ |
| H A D | irq_service_dcn35.c | 196 #define BASE(seg) \ macro
200 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
204 BASE(reg ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
| H A D | irq_service_dcn315.c | 204 #define BASE(seg) \ macro
208 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
212 BASE(reg ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
| H A D | irq_service_dcn302.c | 185 #define BASE(seg) BASE_INNER(seg) macro
188 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
192 BASE(mm ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
| H A D | irq_service_dcn30.c | 208 #define BASE(seg) \ macro
213 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
217 BASE(mm ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
| H A D | irq_service_dcn31.c | 197 #define BASE(seg) \ macro
201 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
205 BASE(reg ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
| H A D | irq_service_dcn314.c | 199 #define BASE(seg) \ macro
203 (BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
207 (BASE(reg ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
| H A D | irq_service_dcn21.c | 201 #define BASE(seg) \ macro
206 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
210 BASE(mm ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn351/ |
| H A D | irq_service_dcn351.c | 175 #define BASE(seg) \ macro
179 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
183 BASE(reg ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/net/ethernet/smsc/ |
| H A D | smc9194.h | 99 #define BASE 2 macro
|
| /linux-master/drivers/ps3/ |
| H A D | ps3av_cmd.c | 489 #define BASE PS3AV_CMD_AUDIO_FS_44K macro
493 [PS3AV_CMD_AUDIO_FS_44K-BASE] = { 6272, 6272, 17836, 17836, 8918 },
494 [PS3AV_CMD_AUDIO_FS_48K-BASE] = { 6144, 6144, 11648, 11648, 5824 },
495 [PS3AV_CMD_AUDIO_FS_88K-BASE] = { 12544, 12544, 35672, 35672, 17836 },
496 [PS3AV_CMD_AUDIO_FS_96K-BASE] = { 12288, 12288, 23296, 23296, 11648 },
497 [PS3AV_CMD_AUDIO_FS_176K-BASE] = { 25088, 25088, 71344, 71344, 35672 },
498 [PS3AV_CMD_AUDIO_FS_192K-BASE] = { 24576, 24576, 46592, 46592, 23296 }
540 ns_val = ps3av_ns_table[PS3AV_CMD_AUDIO_FS_44K-BASE][d];
547 #undef BASE macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_panel_cntl.h | 46 .reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
| H A D | hw_translate_dcn315.c | 52 #define BASE(seg) BASE_INNER(seg) macro
56 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
|
| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| H A D | hw_translate_dcn30.c | 57 #define BASE(seg) BASE_INNER(seg) macro
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
|
| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
| H A D | hw_translate_dcn32.c | 50 #define BASE(seg) BASE_INNER(seg) macro
54 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
|
| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| H A D | hw_translate_dcn20.c | 52 #define BASE(seg) BASE_INNER(seg) macro
56 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
|
| /linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
| H A D | irq_service_dcn303.c | 131 #define BASE(seg) BASE_INNER(seg) macro
134 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
| H A D | irq_service_dcn10.c | 192 #define BASE(seg) \ macro
196 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/irq/dce120/ |
| H A D | irq_service_dce120.c | 95 #define BASE(seg) \ macro
99 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.c | 51 #define BASE(seg) BASE_INNER(seg) macro
53 #define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
|
| /linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
| H A D | irq_service_dcn20.c | 194 #define BASE(seg) \ macro
199 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 249 #define BASE(seg) BASE_INNER(seg) macro
252 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
256 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
260 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
264 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
271 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
275 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
841 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
|
| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| H A D | hw_translate_dcn21.c | 52 #define BASE(seg) BASE_INNER(seg) macro
56 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
|