/haiku/src/add-ons/accelerants/matrox/engine/ |
H A D | mga_dac.c | 29 /*set colour arrays to point to space reserved in shared info*/ 355 switch (target.space) 502 switch (target.space) 523 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE)) 636 switch (target.space) 657 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE))
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H A D | mga_general.c | 969 switch (target->space) 977 LOG(8,("INIT: unknown color space: 0x%08x\n", target->space)); 985 switch (target->space) 993 LOG(8,("INIT: unknown color space: 0x%08x\n", target->space)); 1009 switch (target->space) 1018 LOG(8,("INIT: unknown color space: 0x%08x\n", target->space)); 1024 switch (target->space) [all...] |
H A D | mga_maven.c | 43 /* checkout space needed for hardcursor (if any) */ 363 switch (target.space) 377 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE)) 580 switch (target.space) 594 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE))
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H A D | mga_maventv.c | 75 switch (target.space) 89 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE))
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/haiku/src/add-ons/accelerants/neomagic/ |
H A D | GetModeInfo.c | 56 switch (dm->space)
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H A D | SetDisplayMode.c | 94 switch(target.space) 101 LOG(8,("SETMODE: Invalid colorspace $%08x\n", target.space)); 180 switch(si->dm.space) 232 if (si->dm.space != B_CMAP8) return;
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/haiku/src/add-ons/accelerants/neomagic/engine/ |
H A D | nm_acc.c | 61 switch(si->dm.space)
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H A D | nm_dac.c | 16 /*set colour arrays to point to space reserved in shared info*/ 236 switch (target.space)
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H A D | nm_general.c | 447 switch (target->space) 459 LOG(8,("INIT: unsupported colorspace: 0x%08x\n", target->space)); 464 switch (target->space) 471 LOG(8,("INIT: unsupported colorspace: 0x%08x\n", target->space)); 481 if ((si->ps.card_type < NM2200) && (target->space == B_RGB24)) *acc_mode = false; 502 switch(target->space) 535 switch (target->space) 617 video_pitch, target->space));
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/haiku/src/add-ons/accelerants/nvidia/ |
H A D | GetAccelerantHook.c | 222 if (!si->settings.dma_acc || (si->dm.space == B_CMAP8))
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H A D | GetModeInfo.c | 62 switch (dm->space) 99 switch (dm->space) 122 switch (dm->space)
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H A D | Overlay.c | 184 si->overlay.myBuffer[offset].space = cs; 202 * cardRAM is that apps that try to write beyond the buffer's space get a segfault immediately. 261 * this is done to prevent a large buffer getting created in the space a small buffer 268 * space in between your overlay buffers for instance, so cardRAM is used 'to the max'. 277 /* Check if the new buffer would fit into the space the single old one used here */ 280 /* It does, so we reset to the old size and adresses to prevent the space from shrinking 291 "Overlay: not enough space to 'squeeze' this one in, aborted\n")); 293 /* Reset to the old size to prevent the space from 'growing' if we get here again... */ 304 /* check if we have enough space to setup this new bitmap 309 LOG(4, ("Overlay: Sorry, no more space fo [all...] |
H A D | SetDisplayMode.c | 135 switch(target.space) 159 switch(target2.space) 248 switch(target.space) 255 LOG(8,("SETMODE: Invalid singlehead colour depth 0x%08x\n", target.space)); 309 /* last free adress is end-of-ram minus max space needed for overlay bitmaps */ 360 switch(si->dm.space) 439 if (si->dm.space != B_CMAP8) return;
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/haiku/src/add-ons/accelerants/nvidia/engine/ |
H A D | nv_acc.c | 130 * should point to a DMA definition in CTX register space (which is sort of RAM). 142 * In this space you define the engine command handles (HT_HANDL_XX), which 143 * in turn points to the defines in CTX register space (which is sort of RAM) */ 184 /* first clear the entire RAMHT (hash-table) space to a defined state. It turns 197 /* RAMHT space (hash-table) SETUP FIFO HANDLES */ 203 * (CTX registers are actually a sort of RAM space.) */ 267 * CTX registers are in fact in the same GPU internal RAM space as the engine's 640 switch(si->dm.space)
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H A D | nv_acc_dma.c | 199 /* first clear the entire RAMHT (hash-table) space to a defined state. It turns 212 /* RAMHT (hash-table) space SETUP FIFO HANDLES */ 218 * (CTX registers are actually a sort of RAM space.) */ 296 * CTX registers are in fact in the same GPU internal RAM space as the engine's 526 switch(si->dm.space) 961 * should point to a DMA definition in CTX register space (which is sort of RAM). 977 * In this space you define the engine command handles (HT_HANDL_XX), which 978 * in turn points to the defines in CTX register space (which is sort of RAM) */ 1070 /* note the current free space we have left in the DMA buffer */ 1104 switch(si->dm.space) [all...] |
H A D | nv_bes.c | 751 switch(si->dm.space) 766 /* this space has no alpha bits */ 822 switch(si->dm.space) 837 /* this space has no alpha bits */
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H A D | nv_crtc.c | 47 switch(si->dm.space) 68 /* Doesn't work for other than 32bit space (yet?) */ 69 if (si->dm.space != B_RGB32_LITTLE)
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H A D | nv_crtc2.c | 47 switch(si->dm.space) 68 /* Doesn't work for other than 32bit space (yet?) */ 69 if (si->dm.space != B_RGB32_LITTLE)
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/haiku/src/add-ons/accelerants/radeon/ |
H A D | CP.c | 14 there is enough space in this FIFO. Unfortunately, ATI doesn't speak 21 0xf00 read-only PCI configuration space 30 space. As concurrent threads may do the same, register access should 53 int space; local 55 space = 59 //space = INREG( ai->regs, RADEON_CP_RB_RPTR ) - cp->ring.tail; 61 if( space <= 0 ) 62 space += cp->ring.size; 66 --space; 68 SHOW_FLOW( 3, "head=%ld, tail=%ld, space [all...] |
H A D | GetModeInfo.c | 92 && ai->mode_list[i].space == B_RGB32_LITTLE) {
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H A D | ProposeDisplayMode.c | 97 // convert Be colour space to Radeon data type 98 // returns true, if supported colour space 99 // space - Be colour space 102 bool Radeon_GetFormat( int space, int *format, int *bpp ) argument 104 switch( space ) { 112 SHOW_ERROR( 1, "Unsupported color space (%d)", space ); 173 if( !Radeon_GetFormat( target->space, &format, &bpp )) 235 // but total width has same range as sync start, so leave some space [all...] |
H A D | SetDisplayMode.c | 195 Radeon_GetFormat( mode->space, &format, &bpp ); 453 Radeon_GetFormat( mode.space, &format, &bpp );
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H A D | multimon.c | 164 if( mode->space != 0 || low->space != 0 || high->space != 0
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H A D | overlay.c | 114 // invalidate active colour space 115 si->active_overlay.ob.space = -1; 121 // colour space transformation matrix 150 // set overlay colour space transformation matrix 190 switch( si->pending_overlay.ob.space ) { 214 // get matrix values to convert overlay colour space to RGB 270 si->active_overlay.ob.space = si->pending_overlay.ob.space; 276 uint32 space, uint8 red, uint8 green, uint8 blue ) 286 switch( space ) { 275 colourKey2RGB32( uint32 space, uint8 red, uint8 green, uint8 blue ) argument [all...] |
H A D | overlay_management.c | 52 // color_space - overlay's colour space 67 // cs - overlay's colour space 135 buffer->space = cs; 243 switch (ob->space) {
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