Searched refs:frac (Results 26 - 50 of 91) sorted by path

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/linux-master/drivers/clk/meson/
H A Dclk-pll.h36 struct parm frac; member in struct:meson_clk_pll_data
H A Dg12a.c49 .frac = {
1641 .frac = {
1706 .frac = {
1781 .frac = {
1873 .frac = {
1967 .frac = {
H A Dgxbb.c105 .frac = {
182 .frac = {
236 .frac = {
503 .frac = {
H A Dmeson8b.c76 .frac = {
192 .frac = {
/linux-master/drivers/clk/microchip/
H A Dclk-core.c322 u64 frac; local
337 frac = 0;
342 frac = parent_rate;
343 frac <<= 8;
344 do_div(frac, rate);
345 frac -= (u64)(div << 9);
348 rotrim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : frac;
/linux-master/drivers/clk/mmp/
H A DMakefile6 obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
/linux-master/drivers/clk/pistachio/
H A Dclk.h101 unsigned long long frac; member in struct:pistachio_pll_rate_table
/linux-master/drivers/clk/qcom/
H A Dclk-alpha-pll.c1029 u32 l, frac, alpha_width = pll_alpha_width(pll); local
1032 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
1034 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1304 u32 l, frac, alpha_width = pll_alpha_width(pll); local
1307 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1309 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
2305 u32 l, frac; local
2309 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
2311 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
H A Dclk-rcg.c610 const struct frac_entry *frac = pixel_table; local
613 for (; frac->num; frac++) {
614 request = (req->rate * frac->den) / frac->num;
623 req->rate = (src_rate * frac->num) / frac->den;
635 const struct frac_entry *frac = pixel_table; local
658 for (; frac->num; frac
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H A Dclk-rcg2.c547 const struct frac_entry *frac; local
555 frac = frac_table_810m;
557 frac = frac_table_675m;
559 for (; frac->num; frac++) {
561 request *= frac->den;
562 request = div_s64(request, frac->num);
572 f.m = frac->num;
573 f.n = frac->den;
593 const struct frac_entry *frac; local
784 const struct frac_entry *frac = frac_table_pixel; local
807 const struct frac_entry *frac = frac_table_pixel; local
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/linux-master/drivers/clk/rockchip/
H A Dclk-pll.c159 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
177 u64 frac_rate64 = prate * cur.frac;
200 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
202 rate->postdiv2, rate->dsmpd, rate->frac);
231 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
317 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
319 cur.dsmpd, cur.frac);
320 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
322 rate->dsmpd, rate->frac);
327 (!cur.dsmpd && (rate->frac !
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H A Dclk.c145 struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb); local
146 struct clk_mux *frac_mux = &frac->mux;
152 frac->rate_change_idx =
153 frac->mux_ops->get_parent(&frac_mux->hw);
154 if (frac->rate_change_idx != frac->mux_frac_idx) {
155 frac->mux_ops->set_parent(&frac_mux->hw,
156 frac->mux_frac_idx);
157 frac->rate_change_remuxed = 1;
166 if (frac
215 struct rockchip_clk_frac *frac; local
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H A Dclk.h301 .frac = _frac, \
364 unsigned int frac; member in struct:rockchip_pll_rate_table::__anon365::__anon367
/linux-master/drivers/clk/spear/
H A Dclk-frac-synth.c9 #define pr_fmt(fmt) "clk-frac-synth: " fmt
44 struct clk_frac *frac = to_clk_frac(hw); local
45 struct frac_rate_tbl *rtbl = frac->rtbl;
58 struct clk_frac *frac = to_clk_frac(hw); local
62 frac->rtbl_cnt, &unused);
68 struct clk_frac *frac = to_clk_frac(hw); local
72 if (frac->lock)
73 spin_lock_irqsave(frac->lock, flags);
75 val = readl_relaxed(frac->reg);
77 if (frac
95 struct clk_frac *frac = to_clk_frac(hw); local
127 struct clk_frac *frac; local
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/linux-master/drivers/clk/starfive/
H A Dclk-starfive-jh7110-pll.c16 * NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999.
82 u32 frac; /* frac value should be decimals multiplied by 2^24 */ member in struct:jh7110_pll_preset
96 unsigned int frac; member in struct:jh7110_pll_info::__anon200
119 .frac = JH7110_PLL##_idx##_FRAC_OFFSET, \
150 u32 frac; member in struct:jh7110_pll_regvals
291 regmap_read(regmap, info->offsets.frac, &val);
292 ret->frac = (val & JH7110_PLL_FRAC_MASK) >> JH7110_PLL_FRAC_SHIFT;
310 * dacpd = dsmpd = 1: integer mode, frac valu
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/linux-master/drivers/clk/stm32/
H A Dclk-stm32mp1.c832 u32 reg, frac = 0; local
836 frac = (reg >> FRAC_SHIFT) & FRAC_MASK;
838 return frac;
846 u32 frac, divm, divn; local
857 frac = pll_frac_val(hw);
858 if (frac) {
859 rate_frac = (u64)parent_rate * (u64)frac;
/linux-master/drivers/clk/sunxi-ng/
H A Dccu-sun4i-a10.c84 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
186 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
H A Dccu-sun5i.c84 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
158 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
H A Dccu_mult.c81 if (ccu_frac_helper_is_enabled(&cm->common, &cm->frac))
82 return ccu_frac_helper_read_rate(&cm->common, &cm->frac);
111 if (ccu_frac_helper_has_rate(&cm->common, &cm->frac, rate)) {
112 ccu_frac_helper_enable(&cm->common, &cm->frac);
114 return ccu_frac_helper_set_rate(&cm->common, &cm->frac,
117 ccu_frac_helper_disable(&cm->common, &cm->frac);
H A Dccu_nm.c85 if (ccu_frac_helper_is_enabled(&nm->common, &nm->frac)) {
86 rate = ccu_frac_helper_read_rate(&nm->common, &nm->frac);
142 if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
179 if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
189 ccu_frac_helper_enable(&nm->common, &nm->frac);
191 return ccu_frac_helper_set_rate(&nm->common, &nm->frac,
194 ccu_frac_helper_disable(&nm->common, &nm->frac);
H A Dccu_nm.h28 struct ccu_frac_internal frac; member in struct:ccu_nm
72 .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
97 .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
126 .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
/linux-master/drivers/clk/x86/
H A Dclk-cgu-pll.c22 * rate = (prate * mult + (prate * frac) / frac_div) / div
26 unsigned int div, unsigned int frac, unsigned int frac_div)
32 frate = rate64 * frac;
43 unsigned int div, mult, frac; local
47 frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24);
52 return lgm_pll_calc_rate(prate, mult, div, frac, BIT(24));
25 lgm_pll_calc_rate(unsigned long prate, unsigned int mult, unsigned int div, unsigned int frac, unsigned int frac_div) argument
/linux-master/drivers/clk/xilinx/
H A Dclk-xlnx-clock-wizard.c703 u32 div, frac; local
709 frac = (val >> WZRD_CLKOUT_FRAC_SHIFT) & WZRD_CLKOUT_FRAC_MASK;
711 return mult_frac(parent_rate, 1000, (div * 1000) + frac);
/linux-master/drivers/clk/zynqmp/
H A Dpll.c59 pr_debug("%s() PLL get frac mode failed for %s, ret = %d\n",
87 pr_debug("%s() PLL set frac mode failed for %s, ret = %d\n",
140 unsigned long rate, frac; local
160 frac = (parent_rate * data) / FRAC_DIV;
161 rate = rate + frac;
184 long rate_div, frac, m, f; local
195 frac = (parent_rate * f) / FRAC_DIV;
206 return rate + frac;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c82 static const unsigned int frac = 1000; local
98 (s->data_urgent * frac) / ref_clk_mhz / frac, (s->data_urgent * frac) / ref_clk_mhz % frac,
99 (s->pte_meta_urgent * frac) / ref_clk_mhz / frac, (s->pte_meta_urgent * frac) / ref_clk_mhz % frac,
100 (s->sr_enter * frac) / ref_clk_mh
120 static const unsigned int frac = 1000; local
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