/linux-master/crypto/ |
H A D | drbg.c | 849 struct drbg_string data1, data2; local 863 drbg_string_fill(&data2, V, drbg_statelen(drbg)); 864 list_add_tail(&data2.list, &datalist); 877 drbg_string_fill(&data2, drbg->V, drbg_statelen(drbg)); 878 list_add_tail(&data2.list, &datalist2); 892 struct drbg_string data1, data2; local 902 drbg_string_fill(&data2, drbg->V, drbg_statelen(drbg)); 904 list_add_tail(&data2.list, &datalist); 972 struct drbg_string data1, data2; local 986 drbg_string_fill(&data2, drb [all...] |
/linux-master/drivers/block/ |
H A D | amiflop.c | 901 unsigned long data2; local 904 data2 = data ^ 0x55555555; 905 data |= ((data2 >> 1) | 0x80000000) & (data2 << 1);
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/linux-master/drivers/comedi/drivers/ |
H A D | jr3_pci.c | 383 unsigned int data2 = 0; local 391 read_idm_word(data, size, &pos, &data2); 396 set_u16(hi, data2);
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/linux-master/drivers/cpufreq/ |
H A D | ppc_cbe_cpufreq_pmi.c | 43 pmi_msg.data2 = pmode; 56 ret = pmi_msg.data2; 74 slow_mode = pmi_msg.data2;
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/linux-master/drivers/crypto/bcm/ |
H A D | util.c | 199 * @data2: Second part of data to hash. May be NULL. 200 * @data2_len: Length of data2, in bytes 212 const u8 *data2, unsigned int data2_len, 253 if (data2 && data2_len) { 254 rc = crypto_shash_update(&sdesc->shash, data2, data2_len); 210 do_shash(unsigned char *name, unsigned char *result, const u8 *data1, unsigned int data1_len, const u8 *data2, unsigned int data2_len, const u8 *key, unsigned int key_len) argument
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H A D | util.h | 104 const u8 *data2, unsigned int data2_len,
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/linux-master/drivers/firmware/arm_ffa/ |
H A D | driver.c | 323 .a3 = data->data0, .a4 = data->data1, .a5 = data->data2, 338 data->data2 = ret.a5;
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_vf_error.c | 54 u32 data1, data2, data3; local 79 data2 = adev->virt.vf_errors.data[index] & 0xFFFFFFFF; 82 adev->virt.ops->trans_msg(adev, IDH_LOG_VF_ERROR, data1, data2, data3);
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H A D | amdgpu_virt.h | 91 u32 data1, u32 data2, u32 data3);
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H A D | mmhub_v1_0.c | 452 uint32_t def, data, def1, data1, def2 = 0, data2 = 0; local 458 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); 473 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 490 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 508 if (adev->asic_type != CHIP_RAVEN && def2 != data2) 509 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
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H A D | mmhub_v1_7.c | 459 uint32_t def, data, def1, data1, def2 = 0, data2 = 0; local 464 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); 476 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 492 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 506 if (def2 != data2) 507 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2);
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H A D | mmhub_v2_3.c | 529 uint32_t def, data, def1, data1, def2, data2; local 533 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL); 542 data2 &= ~(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK | 554 data2 |= (DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK | 565 if (def2 != data2) 566 WREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL, data2); 585 int data, data1, data2, data3; local 592 data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL); 608 && !(data2 & (DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
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H A D | mmhub_v3_0.c | 547 uint32_t def1, data1, def2 = 0, data2 = 0; 553 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); 566 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 583 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 598 if (def2 != data2) 599 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2);
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H A D | mxgpu_ai.c | 120 enum idh_request req, u32 data1, u32 data2, u32 data3) { 149 data2); 119 xgpu_ai_mailbox_trans_msg(struct amdgpu_device *adev, enum idh_request req, u32 data1, u32 data2, u32 data3) argument
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H A D | mxgpu_nv.c | 121 enum idh_request req, u32 data1, u32 data2, u32 data3) 143 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW2, data2); 156 enum idh_request req, u32 data1, u32 data2, u32 data3) 162 xgpu_nv_mailbox_trans_msg(adev, req, data1, data2, data3); 120 xgpu_nv_mailbox_trans_msg(struct amdgpu_device *adev, enum idh_request req, u32 data1, u32 data2, u32 data3) argument 155 xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, enum idh_request req, u32 data1, u32 data2, u32 data3) argument
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H A D | uvd_v5_0.c | 682 uint32_t data, data2; local 685 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 717 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 724 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
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H A D | uvd_v6_0.c | 1339 uint32_t data, data2; local 1342 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 1375 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 1382 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
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H A D | uvd_v7_0.c | 1616 uint32_t data, data1, data2, suvd_flags; 1620 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL); 1657 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 1667 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
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/linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dce_dmcu.c | 821 uint32_t header, data1, data2; local 833 data2 = (((uint32_t)data[4]) << 24) | (((uint32_t)data[5]) << 16) | 844 REG_WRITE(MASTER_COMM_DATA_REG3, data2); 858 uint32_t *data2, 869 *data2 = REG_READ(SLAVE_COMM_DATA_REG2); 855 dcn10_get_scp_results(struct dmcu *dmcu, uint32_t *cmd, uint32_t *data1, uint32_t *data2, uint32_t *data3) argument
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/linux-master/drivers/gpu/drm/ast/ |
H A D | ast_post.c | 510 u32 data, data2, patcnt, loop; local 512 data2 = 3; 517 data2 &= data; 518 if (!data2) 526 return data2; 545 u32 data, data2, patcnt, loop; local 547 data2 = 0xffff; 552 data2 &= data; 553 if (!data2) 561 return data2; 1078 u32 data, data2, retry = 0; local 1448 u32 data, data2, retry = 0; local 1868 u32 data, data2, pass, retrycnt; local [all...] |
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/core/ |
H A D | enum.h | 10 u32 data2; member in struct:nvkm_enum
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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
H A D | gf100.c | 573 if (ee && ee->data2) { 574 switch (ee->data2) {
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H A D | runl.c | 370 if (map->data2 == engine->subdev.type && map->inst == engine->subdev.inst) {
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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
H A D | ctxgf100.c | 1096 u32 data[6] = {}, data2[2] = {}; local 1112 data2[0] = (ntpcv << 16); 1113 data2[0] |= (shift << 21); 1114 data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); 1116 data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); 1126 gr->screen_tile_row_offset | data2[0]); 1127 nvkm_wr32(device, 0x419be4, data2[1]);
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H A D | ctxgf117.c | 201 u32 data[6] = {}, data2[2] = {}; local 217 data2[0] = (ntpcv << 16); 218 data2[0] |= (shift << 21); 219 data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); 221 data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); 231 gr->screen_tile_row_offset | data2[0]); 232 nvkm_wr32(device, 0x41bfe4, data2[1]);
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