Searched refs:clk (Results 226 - 250 of 4102) sorted by path

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/linux-master/drivers/phy/samsung/
H A Dphy-exynos4210-usb2.c153 u32 clk; local
182 clk = readl(drv->reg_phy + EXYNOS_4210_UPHYCLK);
183 clk &= ~EXYNOS_4210_UPHYCLK_PHYFSEL_MASK;
184 clk |= drv->ref_reg_val << EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET;
185 writel(clk, drv->reg_phy + EXYNOS_4210_UPHYCLK);
H A Dphy-exynos4x12-usb2.c195 u32 clk; local
197 clk = readl(drv->reg_phy + EXYNOS_4x12_UPHYCLK);
198 clk &= ~EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK;
201 clk = EXYNOS_3250_UPHYCLK_REFCLKSEL;
203 clk |= drv->ref_reg_val << EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET;
204 clk |= EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON;
205 writel(clk, drv->reg_phy + EXYNOS_4x12_UPHYCLK);
/linux-master/drivers/phy/st/
H A Dphy-stih407-usb.c15 #include <linux/clk.h>
/linux-master/drivers/rtc/
H A Drtc-sa1100.h7 struct clk;
19 struct clk *clk; member in struct:sa1100_rtc
/linux-master/drivers/sh/
H A Dpm_runtime.c18 #include <linux/clk.h>
/linux-master/drivers/staging/media/omap4iss/
H A Diss_csiphy.c44 reg |= phy->lanes.clk.pol ? CSI2_COMPLEXIO_CFG_CLOCK_POL : 0;
45 reg |= phy->lanes.clk.pos << CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT;
189 if (lanes->clk.pol > 1 ||
190 lanes->clk.pos > (csi2->phy->max_data_lanes + 1))
193 if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos))
/linux-master/drivers/staging/nvec/
H A Dnvec.h17 #include <linux/clk.h>
139 struct clk *i2c_clk;
/linux-master/drivers/staging/rts5208/
H A Drtsx_card.h997 int switch_ssc_clock(struct rtsx_chip *chip, int clk);
998 int switch_normal_clock(struct rtsx_chip *chip, int clk);
1033 static inline int switch_clock(struct rtsx_chip *chip, int clk) argument
1038 retval = switch_ssc_clock(chip, clk);
1040 retval = switch_normal_clock(chip, clk);
/linux-master/drivers/usb/gadget/udc/
H A Dm66592-udc.h13 #include <linux/clk.h>
465 struct clk *clk; member in struct:m66592
H A Dmv_udc.h221 struct clk *clk; member in struct:mv_udc
H A Domap_udc.h177 struct clk *dc_clk;
178 struct clk *hhc_clk;
H A Dr8a66597-udc.h13 #include <linux/clk.h>
89 struct clk *clk; member in struct:r8a66597
/linux-master/drivers/video/fbdev/matrox/
H A Dmatroxfb_DAC1064.c126 int clk; local
146 for (clk = 65536; clk; --clk) {
150 if (!clk)
615 int clk; local
639 for (clk = 500000; clk; clk--) {
644 if (!clk)
[all...]
H A Dmatroxfb_Ti3026.c299 static int Ti3026_setpclk(struct matrox_fb_info *minfo, int clk) argument
307 f_pll = Ti3026_calcclock(minfo, clk, minfo->max_pixel_clock, &pixin, &pixfeed, &pixpost);
/linux-master/drivers/video/fbdev/omap2/omapfb/dss/
H A Dpll.c8 #include <linux/clk.h>
/linux-master/drivers/video/fbdev/
H A Dpxa168fb.h181 #define CFG_CLKINV(clk) ((clk) << 7)
/linux-master/drivers/video/fbdev/via/
H A Dhw.c1374 int clk)
1383 cur.multiplier = clk / ((f0 / cur.divisor)>>cur.rshift);
1384 f = abs(get_pll_output_frequency(f0, cur) - clk);
1388 if (abs(get_pll_output_frequency(f0, up) - clk) < f)
1390 else if (abs(get_pll_output_frequency(f0, down) - clk) < f)
1398 f = abs(get_pll_output_frequency(f0, cur) - clk);
1399 if (f < abs(get_pll_output_frequency(f0, best) - clk))
1406 static struct via_pll_config get_best_pll_config(int clk) argument
1414 ARRAY_SIZE(cle266_pll_limits), clk);
1420 ARRAY_SIZE(k800_pll_limits), clk);
1373 get_pll_config(struct pll_limit *limits, int size, int clk) argument
1442 viafb_set_vclock(u32 clk, int set_iga) argument
[all...]
/linux-master/drivers/watchdog/
H A Dasm9260_wdt.c9 #include <linux/clk.h>
57 struct clk *clk; member in struct:asm9260_wdt_priv
58 struct clk *clk_ahb;
206 unsigned long clk; local
208 priv->clk = devm_clk_get(priv->dev, "mod");
209 if (IS_ERR(priv->clk)) {
210 dev_err(priv->dev, "Failed to get \"mod\" clk\n");
211 return PTR_ERR(priv->clk);
217 dev_err(priv->dev, "Failed to get \"ahb\" clk\
[all...]
H A Ddigicolor_wdt.c13 #include <linux/clk.h>
26 struct clk *clk; member in struct:dc_wdt
64 dc_wdt_set(wdt, wdog->timeout * clk_get_rate(wdt->clk));
82 dc_wdt_set(wdt, t * clk_get_rate(wdt->clk));
93 return count / clk_get_rate(wdt->clk);
130 wdt->clk = devm_clk_get(dev, NULL);
131 if (IS_ERR(wdt->clk))
132 return PTR_ERR(wdt->clk);
133 dc_wdt_wdd.max_timeout = U32_MAX / clk_get_rate(wdt->clk);
[all...]
/linux-master/include/clocksource/
H A Dtimer-davinci.h12 #include <linux/clk.h>
41 int __init davinci_timer_register(struct clk *clk,
/linux-master/include/linux/
H A Datmel-ssc.h20 struct clk *clk; member in struct:ssc_device
H A Dfsl_devices.h71 struct clk;
85 struct clk *clk; member in struct:fsl_usb2_platform_data
H A Dlantiq.h18 static inline struct clk *clk_get_fpi(void)
/linux-master/include/linux/clk/
H A Dzynq.h14 struct clk *clk_register_zynq_pll(const char *name, const char *parent,
/linux-master/include/linux/dma/
H A Ddw.h12 #include <linux/clk.h>
26 * @clk: hclk clock
35 struct clk *clk; member in struct:dw_dma_chip

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