Searched refs:reg_offset (Results 201 - 225 of 376) sorted by relevance

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/linux-master/arch/powerpc/sysdev/
H A Dtsi108_pci.c45 extern u32 tsi108_read_reg(u32 reg_offset);
46 extern void tsi108_write_reg(u32 reg_offset, u32 val);
/linux-master/drivers/gpio/
H A Dgpio-pcie-idio-24.c125 .reg_offset = (_id) / IDIO_24_NGPIO_PER_REG, \
182 const unsigned int offset = irq_data->reg_offset;
/linux-master/drivers/gpu/drm/loongson/
H A Dlsdc_drv.h78 u32 reg_offset; member in struct:loongson_gfx_desc::__anon713
84 u32 reg_offset; member in struct:loongson_gfx_desc::__anon714
/linux-master/drivers/gpu/drm/amd/include/
H A Dmes_v11_api_def.h537 uint32_t reg_offset; member in struct:WRITE_REG
542 uint32_t reg_offset; member in struct:READ_REG
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v7_11.c34 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
36 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
H A Damdgpu_mes.h280 uint32_t reg_offset; member in struct:mes_misc_op_input::__anon12::__anon13
285 uint32_t reg_offset; member in struct:mes_misc_op_input::__anon12::__anon14
H A Damdgpu_debugfs.c2033 char reg_offset[12]; local
2039 memset(reg_offset, 0, 12);
2045 sprintf(reg_offset, "0x%x\n", adev->reset_info.reset_dump_reg_list[i]);
2047 if (copy_to_user(buf + len, reg_offset, strlen(reg_offset)))
2050 len += strlen(reg_offset);
2066 char reg_offset[11]; local
2071 memset(reg_offset, 0, 11);
2072 if (copy_from_user(reg_offset, buf + len,
2084 if (sscanf(reg_offset, "
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H A Dmes_v11_0.c319 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
324 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
401 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
403 adev->reg_offset[MMHUB_HWIP][0][i];
405 adev->reg_offset[OSSSYS_HWIP][0][i];
H A Dgfx_v6_0.c386 u32 reg_offset, split_equal_to_row_size, *tilemode; local
626 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
627 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
832 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
833 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemod
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H A Dnbio_v4_3.c35 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
37 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
349 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
H A Dnbio_v7_4.c105 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
107 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
347 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
/linux-master/sound/soc/sof/amd/
H A Dacp.h168 unsigned int reg_offset[8]; member in struct:scratch_reg_conf
183 unsigned int reg_offset; member in struct:acp_dsp_stream
/linux-master/drivers/hwtracing/coresight/
H A Dcoresight-cti-sysfs.c261 u32 *pcached_val, int reg_offset)
268 if ((reg_offset >= 0) && cti_active(config)) {
270 val = readl_relaxed(drvdata->base + reg_offset);
284 * if reg_offset >= 0 then write through if enabled.
287 size_t size, u32 *pcached_val, int reg_offset)
302 if ((reg_offset >= 0) && cti_active(config))
303 cti_write_single_reg(drvdata, reg_offset, val);
260 cti_reg32_show(struct device *dev, char *buf, u32 *pcached_val, int reg_offset) argument
286 cti_reg32_store(struct device *dev, const char *buf, size_t size, u32 *pcached_val, int reg_offset) argument
/linux-master/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm64.c24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
49 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
58 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
/linux-master/include/linux/
H A Dirq.h1216 u32 val, int reg_offset)
1219 gc->reg_writel(val, gc->reg_base + reg_offset);
1221 writel(val, gc->reg_base + reg_offset);
1225 int reg_offset)
1228 return gc->reg_readl(gc->reg_base + reg_offset);
1230 return readl(gc->reg_base + reg_offset);
1215 irq_reg_writel(struct irq_chip_generic *gc, u32 val, int reg_offset) argument
1224 irq_reg_readl(struct irq_chip_generic *gc, int reg_offset) argument
/linux-master/drivers/net/ethernet/renesas/
H A Dsh_eth.c350 u16 offset = mdp->reg_offset[enum_index];
361 u16 offset = mdp->reg_offset[enum_index];
378 return mdp->reg_offset[enum_index];
2084 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2208 mdp->reg_offset[TSU_ADRH0] +
2727 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); local
2731 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2732 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr);
2754 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); local
2762 ret = sh_eth_tsu_write_entry(ndev, reg_offset
2771 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); local
2845 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); local
3151 const u16 *reg_offset = NULL; local
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/linux-master/sound/pci/
H A Dintel8x0.c310 unsigned long reg_offset; /* offset to bmaddr */ member in struct:ichdev
640 unsigned long port = ichdev->reg_offset;
692 unsigned long port = ichdev->reg_offset;
791 unsigned long port = ichdev->reg_offset;
828 unsigned long port = ichdev->reg_offset;
1001 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1002 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1008 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1019 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2511 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset,
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H A Dvia82xx.c310 unsigned int reg_offset; member in struct:viadev
965 ((viadev->reg_offset & 0x10) == 0 ? VIA_REG_TYPE_INT_LSAMPLE : 0) |
1031 if (chip->spdif_on && viadev->reg_offset == 0x30)
1042 outb(chip->playback_volume[viadev->reg_offset / 0x10][0],
1044 outb(chip->playback_volume[viadev->reg_offset / 0x10][1],
1172 if (chip->spdif_on && viadev->reg_offset == 0x30) {
1176 } else if (chip->dxs_fixed && viadev->reg_offset < 0x40) {
1180 } else if (chip->dxs_src && viadev->reg_offset < 0x40) {
1246 stream = viadev->reg_offset / 0x10;
1341 stream = viadev->reg_offset /
1408 init_viadev(struct via82xx *chip, int idx, unsigned int reg_offset, int shadow_pos, int direction) argument
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H A Dvia82xx_modem.c205 unsigned int reg_offset; member in struct:viadev
817 static void init_viadev(struct via82xx_modem *chip, int idx, unsigned int reg_offset, argument
820 chip->devs[idx].reg_offset = reg_offset;
822 chip->devs[idx].port = chip->port + reg_offset;
/linux-master/sound/soc/codecs/
H A Dwm8995.c1800 int reg_offset, ret; local
1815 reg_offset = 0;
1819 reg_offset = 0x20;
1865 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,
1870 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_2 + reg_offset,
1874 snd_soc_component_write(component, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);
1876 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_4 + reg_offset,
1880 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_5 + reg_offset,
1887 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,
/linux-master/drivers/soc/mediatek/
H A Dmtk-mutex.c1019 u32 reg_offset, id_offset = 0; local
1042 reg_offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
1045 reg_offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg,
1050 reg = readl_relaxed(mtx->regs + reg_offset);
1056 writel_relaxed(reg, mtx->regs + reg_offset);
/linux-master/drivers/gpu/drm/radeon/
H A Dcik.c2328 u32 reg_offset, split_equal_to_row_size; local
2350 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2351 tile[reg_offset] = 0;
2352 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2353 macrotile[reg_offset] = 0;
2493 for (reg_offset
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/linux-master/drivers/net/ethernet/8390/
H A Detherh.c49 #define EI_SHIFT(x) (ei_local->reg_offset[x])
729 ei_local->reg_offset = etherm_regoffsets;
732 ei_local->reg_offset = etherh_regoffsets;
/linux-master/drivers/staging/media/tegra-video/
H A Dtegra20.c231 const unsigned long reg_offset = 0x42c; local
241 val = readl(apb_misc + reg_offset);
244 writel(val, apb_misc + reg_offset);
/linux-master/sound/soc/rockchip/
H A Drockchip_i2s.c28 u32 reg_offset; member in struct:rk_i2s_pins
447 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
644 .reg_offset = 0xe220,

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