Searched refs:reg (Results 176 - 200 of 1755) sorted by relevance

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/freebsd-11-stable/sys/dev/vxge/vxgehal/
H A Dvxgehal-mrpcim.h69 #define VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(reg) \
74 (reg));
76 #define VXGE_HAL_MRPCIM_ERROR_REG_MASK(reg) \
81 (reg));
83 #define VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(mask, reg) \
88 (reg));
/freebsd-11-stable/sys/arm/nvidia/
H A Das3722.c79 as3722_read(struct as3722_softc *sc, uint8_t reg, uint8_t *val) argument
90 addr = reg;
95 "Error when reading reg 0x%02X, rv: %d\n", reg, rv);
102 int as3722_read_buf(struct as3722_softc *sc, uint8_t reg, uint8_t *buf, argument
114 addr = reg;
119 "Error when reading reg 0x%02X, rv: %d\n", reg, rv);
127 as3722_write(struct as3722_softc *sc, uint8_t reg, uint8_t val) argument
137 data[0] = reg;
149 as3722_write_buf(struct as3722_softc *sc, uint8_t reg, uint8_t *buf, size_t size) argument
173 as3722_modify(struct as3722_softc *sc, uint8_t reg, uint8_t clear, uint8_t set) argument
195 uint8_t reg; local
220 uint32_t reg; local
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/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterContextPOSIX_arm.h35 virtual unsigned GetRegisterSize(unsigned reg);
37 virtual unsigned GetRegisterOffset(unsigned reg);
39 const lldb_private::RegisterInfo *GetRegisterInfoAtIndex(size_t reg) override;
45 const char *GetRegisterName(unsigned reg);
94 bool IsGPR(unsigned reg);
96 bool IsFPR(unsigned reg);
H A DRegisterInfos_x86_64.h44 #define FPR_SIZE(reg) sizeof(((FXSAVE *)nullptr)->reg)
64 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \
66 #reg, alt, sizeof(((GPR *)nullptr)->reg), \
67 GPR_OFFSET(reg), eEncodingUint, eFormatHex, \
69 lldb_##reg##_x86_64 }, \
73 #define DEFINE_FPR(name, reg, kind1, kind2, kind3, kind4) \
75 #name, nullptr, FPR_SIZE(reg), FPR_OFFSET(reg), eEncodingUin
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H A DRegisterContextDarwin_i386.cpp130 #define GPR_OFFSET(reg) \
131 (LLVM_EXTENSION offsetof(RegisterContextDarwin_i386::GPR, reg))
132 #define FPU_OFFSET(reg) \
133 (LLVM_EXTENSION offsetof(RegisterContextDarwin_i386::FPU, reg) + \
135 #define EXC_OFFSET(reg) \
136 (LLVM_EXTENSION offsetof(RegisterContextDarwin_i386::EXC, reg) + \
144 #define DEFINE_GPR(reg, alt) \
145 #reg, alt, sizeof(((RegisterContextDarwin_i386::GPR *) NULL)->reg), \
146 GPR_OFFSET(reg), eEncodingUin
420 GetRegisterInfoAtIndex(size_t reg) argument
495 uint32_t reg = gpr_eax + i; local
592 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; local
709 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; local
864 ConvertRegisterKindToRegisterNumber( lldb::RegisterKind kind, uint32_t reg) argument
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H A DRegisterContextPOSIX_arm.cpp77 bool RegisterContextPOSIX_arm::IsGPR(unsigned reg) { argument
78 return reg <= m_reg_info.last_gpr; // GPR's come first.
81 bool RegisterContextPOSIX_arm::IsFPR(unsigned reg) { argument
82 return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr);
117 unsigned RegisterContextPOSIX_arm::GetRegisterOffset(unsigned reg) { argument
118 assert(reg < m_reg_info.num_registers && "Invalid register number.");
119 return GetRegisterInfo()[reg].byte_offset;
122 unsigned RegisterContextPOSIX_arm::GetRegisterSize(unsigned reg) {
123 assert(reg < m_reg_inf
145 GetRegisterInfoAtIndex(size_t reg) argument
176 GetRegisterName(unsigned reg) argument
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/freebsd-11-stable/sys/dev/nctgpio/
H A Dnctgpio.c150 write_cfg_reg_1(struct nct_softc *sc, uint8_t reg, uint8_t value) argument
153 bus_write_1(sc->portres, 0, reg);
160 read_cfg_reg_1(struct nct_softc *sc, uint8_t reg) argument
165 bus_write_1(sc->portres, 0, reg);
174 read_cfg_reg_2(struct nct_softc *sc, uint8_t reg) argument
178 value = read_cfg_reg_1(sc, reg) << 8;
179 value |= read_cfg_reg_1(sc, reg + 1);
288 uint8_t reg; local
291 reg = nct_ior_addr(pin_num);
293 ior = read_cfg_reg_1(sc, reg);
304 uint8_t reg; local
320 uint8_t reg; local
336 uint8_t reg; local
353 uint8_t reg; local
364 uint8_t reg; local
377 uint8_t reg; local
390 uint8_t reg; local
403 uint8_t reg; local
416 uint8_t reg; local
429 uint8_t reg; local
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/freebsd-11-stable/contrib/gcc/
H A Dunwind-dw2.h48 _Unwind_Word reg; member in union:__anon1396::frame_state_reg_info::__anon1397::__anon1398
60 } reg[DWARF_FRAME_REGISTERS+1]; member in struct:__anon1396::frame_state_reg_info
66 /* The CFA can be described in terms of a reg+offset or a
/freebsd-11-stable/contrib/libexecinfo/
H A Dunwind_arm_ehabi_stub.c57 _Unwind_SetGR(struct _Unwind_Context *context, int reg, _Unwind_Ptr val) argument
59 _Unwind_VRS_Set(context, 0 /*_UVRSC_CORE*/, reg, 0 /*_UVRSD_UINT32*/,
/freebsd-11-stable/lib/libc/sparc64/fpu/
H A Dfpu_reg.S35 .macro ld32 reg
37 ld [%o0], %f\reg
40 .macro st32 reg
42 st %f\reg, [%o0]
45 .macro ld64 reg
47 ldd [%o0], %f\reg
50 .macro st64 reg
52 std %f\reg, [%o0]
/freebsd-11-stable/lib/libthread_db/arch/i386/
H A Dlibpthread_md.c40 pt_reg_to_ucontext(const struct reg *r, ucontext_t *uc)
47 pt_ucontext_to_reg(const ucontext_t *uc, struct reg *r)
107 pt_reg_sstep(struct reg *reg, int step) argument
111 old = reg->r_eflags;
113 reg->r_eflags |= 0x0100;
115 reg->r_eflags &= ~0x0100;
116 return (old != reg->r_eflags); /* changed ? */
/freebsd-11-stable/sys/dev/mii/
H A Dip1000phy.c124 uint32_t gig, reg, speed; local
188 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
189 if (reg & BMSR_LINK) {
301 uint32_t reg; local
303 reg = 0;
305 reg = PHY_READ(sc, IP1000PHY_MII_ANAR);
306 reg &= ~(IP1000PHY_ANAR_PAUSE | IP1000PHY_ANAR_APAUSE);
307 reg |= IP1000PHY_ANAR_NP;
309 reg |= IP1000PHY_ANAR_10T | IP1000PHY_ANAR_10T_FDX |
312 reg |
343 uint32_t reg; local
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/freebsd-11-stable/sys/mips/nlm/hal/
H A Dcpucontrol.h86 nlm_mfcr(uint32_t reg) argument
97 : "=r" (res) : "r"(reg)
104 nlm_mtcr(uint32_t reg, uint64_t value) argument
114 : "r" (value), "r" (reg)
122 nlm_mfcr(uint32_t reg) argument
136 : "r"(reg) : "$8", "$9");
142 nlm_mtcr(uint32_t reg, uint64_t val) argument
161 : :"r"(hi), "r"(lo), "r"(reg)
/freebsd-11-stable/sys/arm/freescale/vybrid/
H A Dvf_dcu4.c224 int reg; local
229 reg = READ4(sc, DCU_INT_STATUS);
230 WRITE4(sc, DCU_INT_STATUS, reg);
287 int reg; local
293 reg = ((sc->sc_info.fb_height) << DELTA_Y_S);
294 reg |= (sc->sc_info.fb_width / 16);
295 WRITE4(sc, DCU_DISP_SIZE, reg);
297 reg = (panel->h_back_porch << BP_H_SHIFT);
298 reg |= (panel->h_pulse_width << PW_H_SHIFT);
299 reg |
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/freebsd-11-stable/sys/arm/ti/
H A Dti_scm.c79 #define ti_scm_read_4(sc, reg) \
80 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
81 #define ti_scm_write_4(sc, reg, val) \
82 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
139 ti_scm_reg_read_4(uint32_t reg, uint32_t *val) argument
144 *val = ti_scm_read_4(ti_scm_sc, reg);
149 ti_scm_reg_write_4(uint32_t reg, uint32_t val) argument
154 ti_scm_write_4(ti_scm_sc, reg, val);
/freebsd-11-stable/sys/arm/include/
H A Dcpu-v4.h57 uint32_t reg; \
58 __asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \
59 return(reg); \
66 uint64_t reg; \
67 __asm __volatile("mrrc\t" _FX(aname): "=r" (reg)); \
68 return(reg); \
80 fname(uint32_t reg) \
82 __asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \
/freebsd-11-stable/stand/i386/boot2/
H A Dsio.S30 movw $SIO_PRT+0x3,%dx # Data format reg
33 subb $0x3,%dl # Divisor latch reg
36 movw $SIO_PRT+0x3,%dx # Data format reg
39 incl %edx # Modem control reg
42 incl %edx # Line status reg
58 movw $SIO_PRT+0x5,%dx # Line status reg
66 subb $0x5,%dl # Transmitter hold reg
74 sio_getc.1: subb $0x5,%dl # Receiver buffer reg
/freebsd-11-stable/sys/mips/rt305x/
H A Drt305x_pci.c360 rt305x_pci_make_addr(int bus, int slot, int func, int reg) argument
364 addr = (((reg & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
365 (func << 8) | (reg & 0xfc) | (1 << 31);
379 u_int reg, int bytes)
388 addr = rt305x_pci_make_addr(bus, slot, func, (reg & ~3));
395 data = RT_READ8(sc, RT305X_PCI_CFGDATA + (reg & 0x3));
398 data = RT_READ16(sc, RT305X_PCI_CFGDATA + (reg & 0x3));
411 u_int reg, uint32_t val, int bytes)
420 addr = rt305x_pci_make_addr(bus, slot, func, (reg & ~3));
427 RT_WRITE8(sc, RT305X_PCI_CFGDATA + (reg
378 rt305x_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) argument
410 rt305x_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int bytes) argument
691 int reg, width; local
934 uint32_t reg, irq, irqidx; local
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/freebsd-11-stable/sys/arm/arm/
H A Dcpufunc_asm_arm11x6.S77 * - value of arg 'reg' Should Be Zero
102 #define Flush_D_cache(reg) \
103 mov reg, #0; /* SBZ */ \
104 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
105 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
107 #define Flush_D_cache(reg) \
108 1: mov reg, #0; /* SBZ */ \
109 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
110 mrc p15, 0, reg, C7, C10, 6;/* Read Cache Dirty Status Register */ \
111 ands reg, re
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/freebsd-11-stable/sys/mips/atheros/
H A Dif_argevar.h68 #define ARGE_WRITE(sc, reg, val) do { \
69 bus_write_4(sc->arge_res, (reg), (val)); \
71 ARGE_READ((sc), (reg)); \
73 #define ARGE_READ(sc, reg) bus_read_4(sc->arge_res, (reg))
75 #define ARGE_SET_BITS(sc, reg, bits) \
76 ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) | (bits))
78 #define ARGE_CLEAR_BITS(sc, reg, bits) \
79 ARGE_WRITE(sc, reg, ARGE_REA
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/freebsd-11-stable/sys/arm/altera/socfpga/
H A Dsocfpga_rstmgr.c89 int reg; local
96 reg = REMAP_MPUZERO;
98 reg |= (remap);
100 reg &= ~(remap);
108 if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) {
111 L3REGS_REMAP, reg);
126 int reg; local
148 reg = READ4(sc, RSTMGR_BRGMODRST);
149 enable = reg & bit ? 0 : 1;
156 reg
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/freebsd-11-stable/sys/dev/etherswitch/
H A Detherswitch.c143 etherswitch_reg_t *reg; local
154 reg = (etherswitch_reg_t *)data;
156 reg->val = ETHERSWITCH_READREG(etherswitch, reg->reg);
161 reg = (etherswitch_reg_t *)data;
163 error = ETHERSWITCH_WRITEREG(etherswitch, reg->reg, reg->val);
185 phyreg->val = ETHERSWITCH_READPHYREG(etherswitch, phyreg->phy, phyreg->reg);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocBase.cpp90 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
93 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
96 LIS->removeInterval(VirtReg->reg);
107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
120 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
136 VRM->assignVirt2Phys(VirtReg->reg,
137 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
148 assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
149 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
153 LIS->removeInterval(SplitVirtReg->reg);
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/freebsd-11-stable/contrib/gcc/config/rs6000/
H A Dlinux-unwind.h242 fs->regs.reg[i].how = REG_SAVED_OFFSET;
243 fs->regs.reg[i].loc.offset = (long) &regs->gpr[i] - new_cfa;
246 fs->regs.reg[CR2_REGNO].how = REG_SAVED_OFFSET;
247 fs->regs.reg[CR2_REGNO].loc.offset = (long) &regs->ccr - new_cfa;
249 fs->regs.reg[LINK_REGISTER_REGNUM].how = REG_SAVED_OFFSET;
250 fs->regs.reg[LINK_REGISTER_REGNUM].loc.offset = (long) &regs->link - new_cfa;
252 fs->regs.reg[ARG_POINTER_REGNUM].how = REG_SAVED_OFFSET;
253 fs->regs.reg[ARG_POINTER_REGNUM].loc.offset = (long) &regs->nip - new_cfa;
274 fs->regs.reg[i + 32].how = REG_SAVED_OFFSET;
275 fs->regs.reg[
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/freebsd-11-stable/sys/sparc64/pci/
H A Dofw_pcibus.c139 uint32_t reg; local
154 reg = CS_READ(PCIR_BRIDGECTL_1, 1);
155 reg |= PCIB_BCR_MASTER_ABORT_MODE | PCIB_BCR_SERR_ENABLE |
160 busno, slot, func, CS_READ(PCIR_BRIDGECTL_1, 1), reg);
162 CS_WRITE(PCIR_BRIDGECTL_1, reg, 1);
164 reg = OFW_PCI_LATENCY;
168 busno, slot, func, CS_READ(PCIR_SECLAT_1, 1), reg);
170 CS_WRITE(PCIR_SECLAT_1, reg, 1);
172 reg = CS_READ(PCIR_MINGNT, 1);
173 if ((int)reg >
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