Searched refs:uint32_t (Results 151 - 175 of 3112) sorted by relevance

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/linux-master/drivers/scsi/mpt3sas/
H A Dmpt3sas_ctl.h119 uint32_t ioc_number;
120 uint32_t port_number;
121 uint32_t max_data_size;
143 uint32_t device:5;
144 uint32_t function:3;
145 uint32_t bus:24;
147 uint32_t word;
149 uint32_t segment_id;
183 uint32_t adapter_type;
184 uint32_t port_numbe
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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gfx.h139 uint16_t pasid, uint32_t flush_type,
166 uint32_t rb_backend_disable;
167 uint32_t user_rb_backend_disable;
168 uint32_t raster_config;
169 uint32_t raster_config_1;
212 uint32_t tile_mode_array[32];
213 uint32_t macrotile_mode_array[16];
219 uint32_t double_offchip_lds_buf;
221 uint32_t db_debug2;
223 uint32_t num_sc_per_s
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H A Ddimgrey_cavefish_reg_init.c33 uint32_t i;
35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
38 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
42 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i]));
43 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(
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H A Dvcn_v2_0.h29 extern void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
33 struct amdgpu_ib *ib, uint32_t flags);
34 extern void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
35 uint32_t val, uint32_t mask);
39 uint32_t reg, uint32_t val);
46 struct amdgpu_ib *ib, uint32_t flags);
47 extern void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
48 uint32_t va
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H A Damdgpu_umsch_mm.h45 uint32_t vmid_mask_mm_vcn;
46 uint32_t vmid_mask_mm_vpe;
47 uint32_t collaboration_mask_vpe;
48 uint32_t logging_vmid;
49 uint32_t engine_mask;
52 uint32_t disable_reset : 1;
53 uint32_t disable_umsch_mm_log : 1;
54 uint32_t use_rs64mem_for_proc_ctx_csa : 1;
55 uint32_t reserved : 29;
57 uint32_t uint32_al
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H A Darct_reg_init.c32 uint32_t i;
34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
42 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(
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/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_i2c_hw.h195 uint32_t DC_I2C_DDC1_ENABLE;
196 uint32_t DC_I2C_DDC1_TIME_LIMIT;
197 uint32_t DC_I2C_DDC1_DATA_DRIVE_EN;
198 uint32_t DC_I2C_DDC1_CLK_DRIVE_EN;
199 uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL;
200 uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
201 uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
202 uint32_t DC_I2C_DDC1_HW_STATUS;
203 uint32_t DC_I2C_SW_DONE_USING_I2C_REG;
204 uint32_t DC_I2C_SW_USE_I2C_REG_RE
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu73_discrete.h45 uint32_t MinVoltage;
47 uint32_t SclkFrequency;
52 uint32_t CgSpllFuncCntl3;
53 uint32_t CgSpllFuncCntl4;
54 uint32_t SpllSpreadSpectrum;
55 uint32_t SpllSpreadSpectrum2;
56 uint32_t CcPwrDynRm;
57 uint32_t CcPwrDynRm1;
71 uint32_t Flags;
72 uint32_t MinVoltag
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H A Dsmu10.h148 uint32_t CurrLevel_ACP : 4;
149 uint32_t CurrLevel_ISP : 4;
150 uint32_t CurrLevel_VCN : 4;
151 uint32_t CurrLevel_LCLK : 4;
152 uint32_t CurrLevel_MP0CLK : 4;
153 uint32_t CurrLevel_FCLK : 4;
154 uint32_t CurrLevel_SOCCLK : 4;
155 uint32_t CurrLevel_DCEFCLK : 4;
157 uint32_t TargLevel_ACP : 4;
158 uint32_t TargLevel_IS
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H A Dsmu7_discrete.h40 uint32_t RefClockFrequency;
41 uint32_t PmTimerP;
42 uint32_t FeatureEnables;
43 uint32_t PreVBlankGap;
44 uint32_t VBlankTimeout;
45 uint32_t TrainTimeGap;
47 uint32_t MvddSwitchTime;
48 uint32_t LongestAcpiTrainTime;
49 uint32_t AcpiDelay;
50 uint32_t G5TrainTim
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H A Dsmu8_fusion.h41 uint32_t MmioAddress;
42 uint32_t MemoryBaseHi;
43 uint32_t MemoryBaseLo;
71 uint32_t DfsBypass;
72 uint32_t Frequency;
79 uint32_t SclkValidMask;
80 uint32_t MaxSclkIndex;
87 uint32_t LclkValidMask;
88 uint32_t MaxLclkIndex;
95 uint32_t EclkValidMas
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/linux-master/drivers/scsi/csiostor/
H A Dcsio_lnode.h66 uint32_t fka_adv;
67 uint32_t fcfi;
94 uint32_t n_link_up; /* Link down */
95 uint32_t n_link_down; /* Link up */
96 uint32_t n_err; /* error */
97 uint32_t n_err_nomem; /* memory not available */
98 uint32_t n_inval_parm; /* Invalid parameters */
99 uint32_t n_evt_unexp; /* unexpected event */
100 uint32_t n_evt_drop; /* dropped event */
101 uint32_t n_rnode_matc
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/linux-master/include/drm/
H A Ddrm_debugfs_crc.h35 uint32_t frame;
36 uint32_t crcs[DRM_MAX_CRC_NR];
65 uint32_t frame, uint32_t *crcs);
68 uint32_t frame, uint32_t *crcs)
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Daux_engine.h45 uint32_t address;
46 uint32_t length;
85 uint32_t ALLOW_AUX_WHEN_HPD_LOW:1;
87 uint32_t raw;
91 uint32_t inst;
96 uint32_t delay;
97 uint32_t max_defer_write_retry;
103 uint32_t current_read_length;
104 uint32_t offset;
112 uint32_t timed_out_retry_au
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/linux-master/drivers/gpu/drm/msm/dsi/
H A Ddsi_phy_28nm.xml.h56 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
58 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
60 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
62 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
64 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i
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/linux-master/drivers/gpu/drm/radeon/
H A Dsmu7_discrete.h39 uint32_t RefClockFrequency;
40 uint32_t PmTimerP;
41 uint32_t FeatureEnables;
42 uint32_t PreVBlankGap;
43 uint32_t VBlankTimeout;
44 uint32_t TrainTimeGap;
46 uint32_t MvddSwitchTime;
47 uint32_t LongestAcpiTrainTime;
48 uint32_t AcpiDelay;
49 uint32_t G5TrainTim
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H A Dnislands_smc.h47 uint32_t TDPLimit;
48 uint32_t NearTDPLimit;
49 uint32_t SafePowerLimit;
50 uint32_t PowerBoostLimit;
55 uint32_t vCG_SPLL_FUNC_CNTL;
56 uint32_t vCG_SPLL_FUNC_CNTL_2;
57 uint32_t vCG_SPLL_FUNC_CNTL_3;
58 uint32_t vCG_SPLL_FUNC_CNTL_4;
59 uint32_t vCG_SPLL_SPREAD_SPECTRUM;
60 uint32_t vCG_SPLL_SPREAD_SPECTRUM_
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h62 uint32_t FClk;
63 uint32_t MemClk;
64 uint32_t Voltage;
70 uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
71 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
72 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
73 uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
74 uint32_t VClocks[NUM_VCN_DPM_LEVELS];
75 uint32_t DClocks[NUM_VCN_DPM_LEVELS];
76 uint32_t SocVoltag
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.h40 uint32_t FClk;
41 uint32_t MemClk;
42 uint32_t Voltage;
50 uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
51 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
52 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
53 uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
54 uint32_t VClocks[NUM_VCN_DPM_LEVELS];
55 uint32_t DClocks[NUM_VCN_DPM_LEVELS];
56 uint32_t SocVoltag
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/linux-master/include/sound/sof/
H A Dcontrol.h84 uint32_t channel; /**< channel map - enum sof_ipc_chmap */
85 uint32_t value;
90 uint32_t index; /**< component source/sink/control index in control */
92 uint32_t uvalue;
100 uint32_t comp_id;
103 uint32_t type; /**< enum sof_ipc_ctrl_type */
104 uint32_t cmd; /**< enum sof_ipc_ctrl_cmd */
105 uint32_t index; /**< control index for comps > 1 control */
109 uint32_t num_elems; /**< in array elems or bytes for data type */
110 uint32_t elems_remainin
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/linux-master/include/linux/
H A Dxxhash.h95 uint32_t xxh32(const void *input, size_t length, uint32_t seed);
147 uint32_t total_len_32;
148 uint32_t large_len;
149 uint32_t v1;
150 uint32_t v2;
151 uint32_t v3;
152 uint32_t v4;
153 uint32_t mem32[4];
154 uint32_t memsiz
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/linux-master/drivers/md/persistent-data/
H A Ddm-bitset.h71 uint32_t current_index;
108 typedef int (*bit_value_fn)(uint32_t index, bool *value, void *context);
110 uint32_t size, bit_value_fn fn, void *context);
123 uint32_t old_nr_entries, uint32_t new_nr_entries,
142 uint32_t index, dm_block_t *new_root);
155 uint32_t index, dm_block_t *new_root);
169 uint32_t index, dm_block_t *new_root, bool *result);
185 uint32_t entries_remaining;
186 uint32_t array_inde
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/linux-master/drivers/media/platform/mediatek/vcodec/decoder/
H A Dvdec_ipi_msg.h44 uint32_t msg_id;
46 uint32_t vpu_inst_addr;
47 uint32_t inst_id;
60 uint32_t msg_id;
72 uint32_t msg_id;
89 uint32_t msg_id;
91 uint32_t vpu_inst_addr;
92 uint32_t inst_id;
94 uint32_t data[3];
111 uint32_t msg_i
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/linux-master/include/linux/iio/common/
H A Dinv_sensors_timestamp.h16 uint32_t clock_period;
17 uint32_t jitter;
18 uint32_t init_period;
38 uint32_t val;
40 uint32_t values[32];
57 uint32_t min_period;
58 uint32_t max_period;
61 uint32_t mult;
62 uint32_t new_mult;
63 uint32_t perio
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/linux-master/fs/jffs2/
H A Djffs2_fs_sb.h52 uint32_t highest_ino;
53 uint32_t check_ino; /* *NEXT* inode to be checked */
64 uint32_t cleanmarker_size; /* Size of an _inline_ CLEANMARKER
67 uint32_t flash_size;
68 uint32_t used_size;
69 uint32_t dirty_size;
70 uint32_t wasted_size;
71 uint32_t free_size;
72 uint32_t erasing_size;
73 uint32_t bad_siz
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