Searched refs:bridge (Results 151 - 175 of 696) sorted by path

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/linux-master/drivers/char/agp/
H A Dintel-agp.c727 struct agp_bridge_data *bridge; local
734 bridge = agp_alloc_bridge();
735 if (!bridge)
738 bridge->capndx = cap_ptr;
740 if (intel_gmch_probe(pdev, NULL, bridge))
745 stand on same host bridge type, this can be
748 bridge->driver = intel_agp_chipsets[i].driver;
753 if (!bridge->driver) {
757 agp_put_bridge(bridge);
761 bridge
811 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); local
823 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); local
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H A Dintel-gtt.c139 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) argument
805 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) argument
814 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) argument
1362 struct agp_bridge_data *bridge)
1387 if (bridge) {
1391 bridge->driver = &intel_fake_agp_driver;
1392 bridge->dev_private_data = &intel_private;
1393 bridge->dev = bridge_pdev;
1410 if (bridge) {
1361 intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, struct agp_bridge_data *bridge) argument
H A Disoch.c60 * node (i.e. a host bridge in combination with the adapters
64 static int agp_3_5_isochronous_node_enable(struct agp_bridge_data *bridge, argument
80 struct pci_dev *td = bridge->dev, *dev;
119 pci_read_config_dword(td, bridge->capndx+AGPNISTAT, &tnistat);
120 pci_read_config_dword(td, bridge->capndx+AGPSTAT, &tstatus);
157 "the AGP 3.0 bridge!\n");
170 pci_read_config_word(td, bridge->capndx+AGPNICMD, &tnicmd);
173 pci_write_config_word(td, bridge->capndx+AGPNICMD, tnicmd);
176 pci_read_config_dword(td, bridge->capndx+AGPNISTAT, &tnistat);
193 "bridge!\
283 agp_3_5_nonisochronous_node_enable(struct agp_bridge_data *bridge, struct agp_3_5_dev *dev_list, unsigned int ndevs) argument
313 agp_3_5_enable(struct agp_bridge_data *bridge) argument
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H A Dnvidia-agp.c206 mask_type = agp_generic_type_to_mask_type(mem->bridge, type);
246 mask_type = agp_generic_type_to_mask_type(mem->bridge, type);
340 struct agp_bridge_data *bridge; local
381 bridge = agp_alloc_bridge();
382 if (!bridge)
385 bridge->driver = &nvidia_driver;
386 bridge->dev_private_data = &nvidia_private;
387 bridge->dev = pdev;
388 bridge->capndx = cap_ptr;
392 bridge
401 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); local
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H A Dparisc-agp.c32 parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr,
101 parisc_agp_create_gatt_table(struct agp_bridge_data *bridge) argument
114 parisc_agp_free_gatt_table(struct agp_bridge_data *bridge) argument
195 parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr, argument
212 parisc_agp_enable(struct agp_bridge_data *bridge, u32 mode) argument
219 command = agp_collect_device_status(bridge, mode, command);
346 struct agp_bridge_data *bridge; local
363 bridge = agp_alloc_bridge();
364 if (!bridge) {
368 bridge
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H A Dsis-agp.c75 static void sis_delayed_enable(struct agp_bridge_data *bridge, u32 mode) argument
81 dev_info(&agp_bridge->dev->dev, "AGP %d.%d bridge\n",
85 command = agp_collect_device_status(bridge, mode, command);
104 if (device->device == bridge->dev->device) {
105 dev_info(&agp_bridge->dev->dev, "SiS delay workaround: giving bridge time to recover\n");
156 static void sis_get_driver(struct agp_bridge_data *bridge) argument
161 if (bridge->dev->device==sis_broken_chipsets[i])
184 struct agp_bridge_data *bridge; local
194 bridge = agp_alloc_bridge();
195 if (!bridge)
214 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); local
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H A Dsworks-agp.c138 static int serverworks_create_gatt_table(struct agp_bridge_data *bridge) argument
188 static int serverworks_free_gatt_table(struct agp_bridge_data *bridge) argument
398 static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode) argument
403 bridge->capndx + PCI_AGP_STATUS,
406 command = agp_collect_device_status(bridge, mode, command);
414 bridge->capndx + PCI_AGP_COMMAND,
449 struct agp_bridge_data *bridge; local
508 bridge = agp_alloc_bridge();
509 if (!bridge)
512 bridge
522 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); local
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H A Duninorth-agp.c228 static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode) argument
233 pci_read_config_dword(bridge->dev,
234 bridge->capndx + PCI_AGP_STATUS,
237 command = agp_collect_device_status(bridge, mode, status);
262 pci_write_config_dword(bridge->dev,
263 bridge->capndx + PCI_AGP_COMMAND,
265 pci_read_config_dword(bridge->dev,
266 bridge->capndx + PCI_AGP_COMMAND,
270 dev_err(&bridge->dev->dev, "can't write UniNorth AGP "
292 struct agp_bridge_data *bridge; local
347 struct agp_bridge_data *bridge; local
369 uninorth_create_gatt_table(struct agp_bridge_data *bridge) argument
449 uninorth_free_gatt_table(struct agp_bridge_data *bridge) argument
606 struct agp_bridge_data *bridge; local
675 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); local
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H A Dvia-agp.c40 printk(KERN_ERR PFX "Unknown aperture size from AGP bridge (0x%x)\n", temp);
424 * VIA's AGP3 chipsets do magick to put the AGP bridge compliant
427 static void check_via_agp3 (struct agp_bridge_data *bridge) argument
431 pci_read_config_byte(bridge->dev, VIA_AGPSEL, &reg);
434 bridge->driver = &via_agp3_driver;
441 struct agp_bridge_data *bridge; local
452 bridge = agp_alloc_bridge();
453 if (!bridge)
456 bridge->dev = pdev;
457 bridge
486 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); local
494 struct agp_bridge_data *bridge = dev_get_drvdata(dev); local
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/linux-master/drivers/cpufreq/
H A DKconfig.x8616 the scaling driver and governor for Sandy bridge processors.
19 scaling driver for Sandy bridge processors.
/linux-master/drivers/cxl/
H A Dacpi.c26 * Find a targets entry (n) in the host bridge interleave list.
554 struct device *bridge; local
582 bridge = pci_root->bus->bridge;
586 * VH mode it will be bound to the CXL host bridge's port
592 dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.uid,
595 dport = devm_cxl_add_dport(root_port, bridge, ctx.uid,
610 * A host bridge is a dport to a CFMWS decode and it is a uport to the
611 * dport (PCIe Root Ports) in the host bridge.
621 struct device *bridge; local
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/linux-master/drivers/cxl/core/
H A Dpci.c808 struct pci_host_bridge *bridge; local
814 bridge = to_pci_host_bridge(dport->dport_dev);
824 if (bridge->native_aer) {
/linux-master/drivers/firmware/efi/
H A Dcper.c396 "PCIe to PCI/PCI-X bridge",
397 "PCI/PCI-X to PCIe bridge",
434 "%s""bridge: secondary_status: 0x%04x, control: 0x%04x\n",
435 pfx, pcie->bridge.secondary_status, pcie->bridge.control);
/linux-master/drivers/fpga/
H A DMakefile32 obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
34 obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
H A Daltera-fpga2sdram.c9 * This driver manages a bridge between an FPGA and the SDRAM used by the ARM
12 * The bridge contains 4 read ports, 4 write ports, and 6 command ports.
26 #include <linux/fpga/fpga-bridge.h>
56 static int alt_fpga2sdram_enable_show(struct fpga_bridge *bridge) argument
58 struct alt_fpga2sdram_data *priv = bridge->priv;
73 static int alt_fpga2sdram_enable_set(struct fpga_bridge *bridge, bool enable) argument
75 return _alt_fpga2sdram_enable_set(bridge->priv, enable);
90 { .compatible = "altr,socfpga-fpga2sdram-bridge" },
121 /* Get f2s bridge configuration saved in handoff register */
133 if (!of_property_read_u32(dev->of_node, "bridge
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H A Daltera-freeze-bridge.c13 #include <linux/fpga/fpga-bridge.h>
101 dev_dbg(dev, "%s bridge already disabled %d\n",
105 dev_err(dev, "%s bridge not enabled %d\n", __func__, status);
138 dev_dbg(dev, "%s bridge already enabled %d\n",
142 dev_err(dev, "%s bridge not frozen %d\n", __func__, status);
161 * enable = 1 : allow traffic through the bridge
162 * enable = 0 : disable traffic through the bridge
164 static int altera_freeze_br_enable_set(struct fpga_bridge *bridge, argument
167 struct altera_freeze_br_data *priv = bridge->priv;
168 struct fpga_image_info *info = bridge
190 altera_freeze_br_enable_show(struct fpga_bridge *bridge) argument
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H A Daltera-hps2fpga.c8 * fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters
23 #include <linux/fpga/fpga-bridge.h>
50 static int alt_hps2fpga_enable_show(struct fpga_bridge *bridge) argument
52 struct altera_hps2fpga_data *priv = bridge->priv;
67 /* bring bridge out of reset */
75 /* Allow bridge to be visible to L3 masters or not */
93 static int alt_hps2fpga_enable_set(struct fpga_bridge *bridge, bool enable) argument
95 return _alt_hps2fpga_enable_set(bridge->priv, enable);
118 { .compatible = "altr,socfpga-hps2fpga-bridge",
120 { .compatible = "altr,socfpga-lwhps2fpga-bridge",
196 struct fpga_bridge *bridge = platform_get_drvdata(pdev); local
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H A Ddfl-fme-br.c17 #include <linux/fpga/fpga-bridge.h>
28 static int fme_bridge_enable_set(struct fpga_bridge *bridge, bool enable) argument
30 struct fme_br_priv *priv = bridge->priv;
107 MODULE_ALIAS("platform:dfl-fme-bridge");
H A Ddfl-fme-pr.c24 #include <linux/fpga/fpga-bridge.h>
151 * reenabling the bridge to clear things out between acceleration runs.
222 * dfl_fme_create_bridge - create fme fpga bridge platform device as child
225 * @port_id: port id for the bridge to be created.
227 * Return: bridge platform device if successful, and error code otherwise.
267 * dfl_fme_destroy_bridge - destroy fpga bridge platform device
268 * @fme_br: fme bridge to destroy
276 * dfl_fme_destroy_bridges - destroy all fpga bridge platform device
387 /* Initialize the region and bridge sub device list */
407 /* Create bridge fo
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H A Dfpga-bridge.c8 #include <linux/fpga/fpga-bridge.h>
23 * fpga_bridge_enable - Enable transactions on the bridge
25 * @bridge: FPGA bridge
29 int fpga_bridge_enable(struct fpga_bridge *bridge) argument
31 dev_dbg(&bridge->dev, "enable\n");
33 if (bridge->br_ops->enable_set)
34 return bridge->br_ops->enable_set(bridge, 1);
41 * fpga_bridge_disable - Disable transactions on the bridge
47 fpga_bridge_disable(struct fpga_bridge *bridge) argument
61 struct fpga_bridge *bridge; local
144 fpga_bridge_put(struct fpga_bridge *bridge) argument
165 struct fpga_bridge *bridge; local
189 struct fpga_bridge *bridge; local
212 struct fpga_bridge *bridge, *next; local
240 struct fpga_bridge *bridge; local
270 struct fpga_bridge *bridge; local
288 struct fpga_bridge *bridge = to_fpga_bridge(dev); local
296 struct fpga_bridge *bridge = to_fpga_bridge(dev); local
332 struct fpga_bridge *bridge; local
398 fpga_bridge_unregister(struct fpga_bridge *bridge) argument
413 struct fpga_bridge *bridge = to_fpga_bridge(dev); local
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H A Dfpga-region.c8 #include <linux/fpga/fpga-bridge.h>
H A Dof-fpga-region.c8 #include <linux/fpga/fpga-bridge.h>
77 * Create a list of bridges including the parent bridge and the bridges
96 /* If parent is a bridge, add to list */
100 /* -EBUSY means parent is a bridge that is under use. Give up. */
104 /* Zero return code means parent was a bridge and was added to list. */
122 /* If parent bridge is in list, skip it. */
128 /* If node is a bridge, get it and add to list */
/linux-master/drivers/fpga/tests/
H A DMakefile6 obj-$(CONFIG_FPGA_KUNIT_TESTS) += fpga-mgr-test.o fpga-bridge-test.o fpga-region-test.o
H A Dfpga-bridge-test.c12 #include <linux/fpga/fpga-bridge.h>
21 struct fpga_bridge *bridge; member in struct:bridge_ctx
26 static int op_enable_set(struct fpga_bridge *bridge, bool enable) argument
28 struct bridge_stats *stats = bridge->priv;
36 * Fake FPGA bridge that implements only the enable_set op to track
44 * register_test_bridge() - Register a fake FPGA bridge for testing.
47 * Return: Context of the newly registered FPGA bridge.
59 ctx->bridge = fpga_bridge_register(&ctx->pdev->dev, "Fake FPGA bridge", &fake_bridge_ops,
61 KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->bridge));
75 struct fpga_bridge *bridge; local
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H A Dfpga-region-test.c11 #include <linux/fpga/fpga-bridge.h>
30 struct fpga_bridge *bridge; member in struct:test_ctx
57 static int op_enable_set(struct fpga_bridge *bridge, bool enable) argument
59 struct bridge_stats *stats = bridge->priv;
70 * Fake FPGA bridge that implements only enable_set op to count the number
79 struct fpga_bridge *bridge = region->priv; local
81 return fpga_bridge_get_to_list(bridge->dev.parent, region->info, &region->bridge_list);
138 * The configuration used in this test suite uses a single bridge to
162 ctx->bridge = fpga_bridge_register(&ctx->bridge_pdev->dev, "Fake FPGA Bridge",
164 KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->bridge));
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