Searched refs:barrier (Results 126 - 150 of 545) sorted by path
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| /linux-master/arch/hexagon/kernel/ |
| H A D | smp.c | 105 /* Possible barrier here */
186 barrier();
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| /linux-master/arch/loongarch/include/asm/ |
| H A D | atomic.h | 11 #include <asm/barrier.h>
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| H A D | barrier.h | 12 * Bit3: barrier for previous read (0: true, 1: false)
13 * Bit2: barrier for previous write (0: true, 1: false)
14 * Bit1: barrier for succeeding read (0: true, 1: false)
15 * Bit0: barrier for succeeding write (0: true, 1: false)
17 * Hint 0x700: barrier for "read after read" from the same address
60 #define __smp_mb__before_atomic() barrier()
61 #define __smp_mb__after_atomic() barrier()
137 #include <asm-generic/barrier.h>
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| H A D | bitops.h | 14 #include <asm/barrier.h>
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| H A D | cmpxchg.h | 10 #include <asm/barrier.h>
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| H A D | futex.h | 11 #include <asm/barrier.h>
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| H A D | vdso.h | 14 #include <asm/barrier.h>
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| /linux-master/arch/loongarch/include/asm/vdso/ |
| H A D | processor.h | 10 #define cpu_relax() barrier()
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| /linux-master/arch/loongarch/kernel/ |
| H A D | perf_event.c | 379 barrier();
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| /linux-master/arch/m68k/amiga/ |
| H A D | config.c | 692 barrier();
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| /linux-master/arch/m68k/atari/ |
| H A D | atakeyb.c | 553 barrier();
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| /linux-master/arch/m68k/include/asm/ |
| H A D | atomic.h | 8 #include <asm/barrier.h>
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| H A D | bitops.h | 16 #include <asm/barrier.h>
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| H A D | processor.h | 163 #define cpu_relax() barrier()
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| /linux-master/arch/microblaze/include/asm/ |
| H A D | barrier.h | 11 #include <asm-generic/barrier.h>
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| H A D | processor.h | 21 # define cpu_relax() barrier()
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| /linux-master/arch/mips/include/asm/ |
| H A D | atomic.h | 20 #include <asm/barrier.h>
238 * completion barrier at 2: above, which is needed due to the \
240 * such, we don't need to emit another barrier here. \
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| H A D | barrier.h | 86 # define __smp_mb() barrier()
87 # define __smp_rmb() barrier()
88 # define __smp_wmb() barrier()
92 * When LL/SC does imply order, it must also be a compiler barrier to avoid the
124 * a completion barrier immediately preceding the LL instruction. Therefore we
125 * can skip emitting a barrier from __smp_mb__before_atomic().
140 #include <asm-generic/barrier.h>
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| H A D | bitops.h | 20 #include <asm/barrier.h>
113 * not contain a memory barrier, so if it is used for locking purposes,
206 * It also implies a memory barrier.
221 * It also implies a memory barrier.
258 * It also implies a memory barrier.
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| H A D | bmips.h | 97 barrier();
123 barrier();
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| H A D | futex.h | 16 #include <asm/barrier.h>
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| H A D | io.h | 20 #include <asm/barrier.h>
83 * barriers defined in <asm/barrier.h>. API pinched from PowerPC,
193 #define war_io_reorder_wmb() barrier()
196 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \
204 if (barrier) \
245 if (barrier) \
277 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax) \
284 if (barrier) \
308 if (barrier) \
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| H A D | mmiowb.h | 5 #include <asm/barrier.h>
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| H A D | mmu_context.h | 20 #include <asm/barrier.h>
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| /linux-master/arch/mips/include/asm/octeon/ |
| H A D | cvmx-fpa.h | 234 barrier();
257 * we free this buffer. This also serves as a barrier to
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