Searched refs:reg_value (Results 101 - 121 of 121) sorted by relevance

12345

/linux-master/drivers/media/i2c/
H A Dov5640.c370 struct reg_value { struct
399 const struct reg_value *reg_data;
546 static const struct reg_value ov5640_init_setting[] = {
624 static const struct reg_value ov5640_setting_low_res[] = {
639 static const struct reg_value ov5640_setting_720P_1280_720[] = {
654 static const struct reg_value ov5640_setting_1080P_1920_1080[] = {
678 static const struct reg_value ov5640_setting_QSXGA_2592_1944[] = {
1715 const struct reg_value *regs, unsigned int regnum)
/linux-master/drivers/iio/temperature/
H A Dmlx90635.c268 s32 *reg_value)
284 *reg_value = (read << 16) | (value & 0xffff);
267 mlx90635_read_ee_register(struct regmap *regmap, u16 reg_lsb, s32 *reg_value) argument
H A Dmlx90632.c648 s32 *reg_value)
664 *reg_value = (read << 16) | (value & 0xffff);
647 mlx90632_read_ee_register(struct regmap *regmap, u16 reg_lsb, s32 *reg_value) argument
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_0.c2568 uint32_t reg_value = 0; local
2570 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2572 if (reg_value)
2573 sdma_v4_0_get_ras_error_count(reg_value,
H A Dmes_v11_0.c325 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
H A Dvcn_v4_0.c2146 uint32_t poison_stat = 0, reg_value = 0; local
2150 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);
2151 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
H A Dvcn_v2_5.c1947 uint32_t poison_stat = 0, reg_value = 0; local
1951 reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS);
1952 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
H A Dgfx_v9_0.c4417 ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value;
4445 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value;
4473 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value;
6731 uint32_t reg_value; local
6745 reg_value =
6747 if (reg_value)
6750 j, k, reg_value,
H A Damdgpu_mes.c836 op_input.write_reg.reg_value = val;
H A Damdgpu_psp.c1111 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu10_hwmgr.c1280 uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP); local
1282 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
/linux-master/drivers/net/wireless/marvell/mwifiex/
H A Dsta_ioctl.c1244 u32 reg_offset, u32 reg_value)
1250 reg_rw.value = reg_value;
1243 mwifiex_reg_write(struct mwifiex_private *priv, u32 reg_type, u32 reg_offset, u32 reg_value) argument
H A Dmain.h1503 u32 reg_offset, u32 reg_value);
/linux-master/drivers/media/dvb-frontends/
H A Dcxd2841er.c358 u32 reg_value = 0; local
367 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
368 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
370 "%s(): reg_value is out of range\n", __func__);
373 data[0] = (u8)((reg_value >> 16) & 0x0F);
374 data[1] = (u8)((reg_value >> 8) & 0xFF);
375 data[2] = (u8)(reg_value & 0xFF);
/linux-master/drivers/accel/habanalabs/gaudi/
H A Dgaudi.c8821 struct hl_sync_to_engine_map *map, u32 reg_value,
8830 if (reg_value == 0 || reg_value == 0xffffffff)
8832 reg_value -= lower_32_bits(CFG_BASE);
8840 entry->sync_id = reg_value;
8841 hash_add(map->tb, &entry->node, reg_value);
8851 u32 reg_value; local
8856 reg_value = RREG32(sds->props[SP_TPC0_CFG_SO] +
8859 rc = gaudi_add_sync_to_engine_map_entry(map, reg_value,
8869 reg_value
8820 gaudi_add_sync_to_engine_map_entry( struct hl_sync_to_engine_map *map, u32 reg_value, enum hl_sync_engine_type engine_type, u32 engine_id) argument
[all...]
/linux-master/drivers/scsi/arm/
H A Dacornscsi.c614 unsigned char reg_value; member in struct:sync_xfer_tbl
637 if (syncxfer == sync_xfer_table[i].reg_value)
674 return sync_xfer_table[round_period(period)].reg_value |
/linux-master/drivers/iio/accel/
H A Dbmc150-accel-core.c187 u8 reg_value; member in struct:__anon23
224 bmc150_accel_sleep_value_table[i].reg_value;
/linux-master/drivers/scsi/hisi_sas/
H A Dhisi_sas_v2_hw.c2772 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, local
2775 switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2794 reg_value = hisi_sas_read32(hisi_hba,
2796 if (reg_value & BIT(phy_no)) {
/linux-master/drivers/tty/
H A Dsynclink_gt.c4723 unsigned int reg_value; local
4749 reg_value = rd_reg32(info, TDCSR);
4752 if (reg_value & BIT0)
4755 /* add tx FIFO count = reg_value[15..8] */
4756 total_count += (reg_value >> 8) & 0xff;
/linux-master/drivers/net/ethernet/intel/i40e/
H A Di40e_adminq_cmd.h1856 __le32 reg_value; member in struct:i40e_aqc_phy_register_access
H A Di40e_common.c5345 cmd->reg_value = cpu_to_le32(reg_val);
5398 *reg_val = le32_to_cpu(cmd->reg_value);

Completed in 663 milliseconds

12345