Searched refs:reg_base (Results 101 - 125 of 407) sorted by relevance

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/linux-master/drivers/net/can/cc770/
H A Dcc770_isa.c114 return readb(priv->reg_base + reg);
120 writeb(val, priv->reg_base + reg);
125 return inb((unsigned long)priv->reg_base + reg);
131 outb(val, (unsigned long)priv->reg_base + reg);
137 unsigned long base = (unsigned long)priv->reg_base;
152 unsigned long base = (unsigned long)priv->reg_base;
203 priv->reg_base = base;
208 priv->reg_base = (void __iomem *)port[idx];
270 dev_info(&pdev->dev, "device registered (reg_base=0x%p, irq=%d)\n",
271 priv->reg_base, de
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/linux-master/drivers/net/can/sja1000/
H A Dems_pci.c135 return readb(priv->reg_base + (port * 4));
141 writeb(val, priv->reg_base + (port * 4));
155 return readb(priv->reg_base + port);
161 writeb(val, priv->reg_base + port);
173 return readb(priv->reg_base + port);
179 writeb(val, priv->reg_base + port);
354 priv->reg_base = card->base_addr + EMS_PCI_V1_CAN_BASE_OFFSET
360 priv->reg_base = card->base_addr + EMS_PCI_V2_CAN_BASE_OFFSET
366 priv->reg_base = card->base_addr + EMS_PCI_V3_CAN_BASE_OFFSET
408 i + 1, priv->reg_base, de
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H A Dpeak_pci.c163 void __iomem *reg_base; /* first channel base address */ member in struct:peak_pciec_card
405 int c = (priv->reg_base - card->reg_base) / PEAK_PCI_CHAN_SIZE;
460 card->reg_base = priv->reg_base;
531 return readb(priv->reg_base + (port << 2));
537 writeb(val, priv->reg_base + (port << 2));
556 void __iomem *cfg_base, *reg_base; local
596 reg_base = pci_iomap(pdev, 1, PEAK_PCI_CHAN_SIZE * channels);
597 if (!reg_base) {
745 void __iomem *reg_base = priv->reg_base; local
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H A Dtscan1.c68 return inb((unsigned long)priv->reg_base + reg);
74 outb(val, (unsigned long)priv->reg_base + reg);
140 priv->reg_base = (void __iomem *)sja1000_base;
173 sja1000_base = (unsigned long)priv->reg_base;
/linux-master/sound/soc/codecs/
H A Drt715-sdca.c171 unsigned int reg_base = p->reg_base, k_changed = 0; local
188 ret = regmap_write(rt715->mbq_regmap, reg_base + i,
192 __func__, reg_base + i, gain_val);
207 unsigned int reg_base = p->reg_base, i, k_changed = 0; local
224 reg = i < 7 ? reg_base + i : (reg_base - 1) | BIT(15);
266 unsigned int reg_base = p->reg_base, local
291 unsigned int reg_base = p->reg_base; local
328 unsigned int reg_base = p->reg_base; local
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/linux-master/drivers/gpu/drm/i915/gvt/
H A Dinterrupt.c41 i915_reg_t reg_base; member in struct:intel_gvt_irq_info
173 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)
351 regbase_to_iir(i915_mmio_reg_offset(info->reg_base)))
353 regbase_to_ier(i915_mmio_reg_offset(info->reg_base)));
380 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);
386 i915_mmio_reg_offset(up_irq_info->reg_base));
388 i915_mmio_reg_offset(up_irq_info->reg_base));
462 unsigned int reg_base; local
469 reg_base = i915_mmio_reg_offset(info->reg_base);
533 u32 reg_base; local
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/linux-master/drivers/clk/xilinx/
H A Dxlnx_vcu.c230 void __iomem *reg_base; member in struct:vcu_pll
237 void __iomem *base = pll->reg_base;
254 void __iomem *reg_base)
263 vcu_pll_ctrl = xvcu_read(reg_base, VCU_PLL_CTRL);
287 void __iomem *base = pll->reg_base;
329 void __iomem *base = pll->reg_base;
350 void __iomem *base = pll->reg_base;
381 void __iomem *base = pll->reg_base;
400 void __iomem *reg_base,
420 pll->reg_base
251 xvcu_register_pll_post(struct device *dev, const char *name, const struct clk_hw *parent_hw, void __iomem *reg_base) argument
399 xvcu_register_pll(struct device *dev, void __iomem *reg_base, const char *name, const char *parent, unsigned long flags) argument
528 void __iomem *reg_base = xvcu->vcu_slcr_ba; local
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/linux-master/drivers/media/rc/img-ir/
H A Dimg-ir.h138 * @reg_base: Iomem base address of IR register block.
148 void __iomem *reg_base; member in struct:img_ir_priv
160 iowrite32(data, priv->reg_base + reg_offs);
166 return ioread32(priv->reg_base + reg_offs);
/linux-master/drivers/rtc/
H A Drtc-pic32.c58 void __iomem *reg_base; member in struct:pic32_rtc_dev
101 void __iomem *base = pdata->reg_base;
119 void __iomem *base = pdata->reg_base;
135 void __iomem *base = pdata->reg_base;
174 void __iomem *base = pdata->reg_base;
194 void __iomem *base = pdata->reg_base;
226 void __iomem *base = pdata->reg_base;
243 void __iomem *base = pdata->reg_base;
267 void __iomem *base = pdata->reg_base;
311 pdata->reg_base
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/linux-master/drivers/irqchip/
H A Dirq-loongson-liointc.c106 writel(readl(gc->reg_base + offset) | mask,
107 gc->reg_base + offset);
109 writel(readl(gc->reg_base + offset) & ~mask,
110 gc->reg_base + offset);
151 priv->int_pol = readl(gc->reg_base + LIOINTC_REG_INTC_POL);
152 priv->int_edge = readl(gc->reg_base + LIOINTC_REG_INTC_EDGE);
163 writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
166 writeb(priv->map_cache[i], gc->reg_base + i);
167 writel(priv->int_pol, gc->reg_base + LIOINTC_REG_INTC_POL);
168 writel(priv->int_edge, gc->reg_base
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/linux-master/drivers/net/ethernet/marvell/octeontx2/af/
H A Dmbox.c48 mbox->reg_base = NULL;
57 void *reg_base, int direction, int ndevs)
117 mbox->reg_base = reg_base;
131 void *reg_base, int direction, int ndevs)
136 err = otx2_mbox_setup(mbox, pdev, reg_base, direction, ndevs);
159 struct pci_dev *pdev, void *reg_base,
165 err = otx2_mbox_setup(mbox, pdev, reg_base, direction, ndevs);
259 intr_val = readq((void __iomem *)mbox->reg_base +
266 writeq(intr_val, (void __iomem *)mbox->reg_base
56 otx2_mbox_setup(struct otx2_mbox *mbox, struct pci_dev *pdev, void *reg_base, int direction, int ndevs) argument
130 otx2_mbox_init(struct otx2_mbox *mbox, void *hwbase, struct pci_dev *pdev, void *reg_base, int direction, int ndevs) argument
158 otx2_mbox_regions_init(struct otx2_mbox *mbox, void **hwbase, struct pci_dev *pdev, void *reg_base, int direction, int ndevs, unsigned long *pf_bmap) argument
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/linux-master/drivers/dma/idxd/
H A Ddevice.c25 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
28 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
35 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
38 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
312 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
316 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
350 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
353 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
435 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
446 gensts.bits = ioread32(idxd->reg_base
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/linux-master/drivers/usb/musb/
H A Dda8xx.c87 void __iomem *reg_base = musb->ctrl_base; local
94 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
97 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
106 void __iomem *reg_base = musb->ctrl_base; local
108 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
111 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
226 void __iomem *reg_base = musb->ctrl_base; local
239 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
243 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
259 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_RE
358 void __iomem *reg_base = musb->ctrl_base; local
451 void __iomem *reg_base = musb->ctrl_base; local
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/linux-master/drivers/crypto/cavium/cpt/
H A Dcptpf.h50 void __iomem *reg_base; /* Register start address */ member in struct:cpt_device
H A Dcptvf_mbox.c11 cpt_write_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 0),
13 cpt_write_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 1),
26 mbx.msg = cpt_read_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 0));
27 mbx.data = cpt_read_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 1));
/linux-master/include/video/
H A Dpxa168fb.h67 void __iomem *reg_base; member in struct:pxa168fb_info
/linux-master/drivers/net/ethernet/cavium/common/
H A Dcavium_ptp.h19 void __iomem *reg_base; member in struct:cavium_ptp
/linux-master/drivers/crypto/marvell/octeontx/
H A Dotx_cptvf_mbox.c79 writeq(mbx->msg, cptvf->reg_base + OTX_CPT_VFX_PF_MBOXX(0, 0));
80 writeq(mbx->data, cptvf->reg_base + OTX_CPT_VFX_PF_MBOXX(0, 1));
92 mbx.msg = readq(cptvf->reg_base + OTX_CPT_VFX_PF_MBOXX(0, 0));
93 mbx.data = readq(cptvf->reg_base + OTX_CPT_VFX_PF_MBOXX(0, 1));
/linux-master/drivers/clocksource/
H A Dexynos_mct.c77 static void __iomem *reg_base; variable
98 writel_relaxed(value, reg_base + offset);
148 if (readl_relaxed(reg_base + stat_addr) & mask) {
149 writel_relaxed(mask, reg_base + stat_addr);
161 reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
179 u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
183 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
184 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
200 return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
267 tcon = readl_relaxed(reg_base
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/linux-master/sound/soc/loongson/
H A Dloongson_i2s.h62 void __iomem *reg_base; member in struct:loongson_i2s
H A Dloongson_i2s_pci.c99 i2s->reg_base = pcim_iomap_table(pdev)[0];
100 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->reg_base,
111 tx_data->order_addr = i2s->reg_base + LS_I2S_TX_ORDER;
114 rx_data->order_addr = i2s->reg_base + LS_I2S_RX_ORDER;
/linux-master/drivers/clk/visconti/
H A Dpll.h17 void __iomem *reg_base; member in struct:visconti_pll_provider
/linux-master/drivers/crypto/marvell/octeontx2/
H A Dotx2_cpt_common.h132 static inline void otx2_cpt_write64(void __iomem *reg_base, u64 blk, u64 slot, argument
135 writeq_relaxed(val, reg_base +
139 static inline u64 otx2_cpt_read64(void __iomem *reg_base, u64 blk, u64 slot, argument
142 return readq_relaxed(reg_base +
/linux-master/drivers/pci/controller/cadence/
H A Dpcie-cadence.h293 * @reg_base: IO mapped register base
304 void __iomem *reg_base; member in struct:cdns_pcie
394 writel(value, pcie->reg_base + reg);
399 return readl(pcie->reg_base + reg);
446 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
454 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
461 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
470 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;
478 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;
486 writel(value, pcie->reg_base
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/linux-master/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_dev.c202 mdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
203 if (IS_ERR(mdev->reg_base)) {
205 err = PTR_ERR(mdev->reg_base);
206 mdev->reg_base = NULL;
220 mdev->funcs = komeda_identify(mdev->reg_base, &mdev->chip);
308 if (mdev->reg_base) {
309 devm_iounmap(dev, mdev->reg_base);
310 mdev->reg_base = NULL;

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