Searched refs:clock (Results 101 - 125 of 1865) sorted by relevance

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/linux-master/drivers/media/platform/qcom/camss/
H A Dcamss.c39 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
52 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
67 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
85 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
103 .clock = { "top_ahb", "ahb", "ispif_ahb",
116 .clock = { "top_ahb", "vfe0", "csi_vfe0",
140 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
153 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
166 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer" },
181 .clock
965 camss_enable_clocks(int nclocks, struct camss_clock *clock, struct device *dev) argument
993 camss_disable_clocks(int nclocks, struct camss_clock *clock) argument
[all...]
/linux-master/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-is-i2c.c20 struct clk *clock; member in struct:fimc_is_i2c
48 isp_i2c->clock = devm_clk_get(&pdev->dev, "i2c_isp");
49 if (IS_ERR(isp_i2c->clock)) {
50 dev_err(&pdev->dev, "failed to get the clock\n");
51 return PTR_ERR(isp_i2c->clock);
97 clk_disable_unprepare(isp_i2c->clock);
105 return clk_prepare_enable(isp_i2c->clock);
/linux-master/drivers/clocksource/
H A Dtimer-ti-32k.c83 struct clk *clock; local
86 clock = of_clk_get_by_name(np->parent, name);
87 if (IS_ERR(clock)) {
88 /* Only some SoCs have a separate interface clock */
89 if (PTR_ERR(clock) == -EINVAL && !strncmp("ick", name, 3))
92 pr_warn("%s: could not get clock %s %li\n",
93 __func__, name, PTR_ERR(clock));
97 error = clk_prepare_enable(clock);
/linux-master/drivers/clk/ti/
H A Dadpll.c184 "clock-output-names",
199 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, argument
207 d->clocks[index].clk = clock;
214 dev_warn(d->dev, "clock %s con_id lookup may fail\n",
217 cl = clkdev_create(clock, con_id, NULL);
222 dev_warn(d->dev, "no con_id for clock %s\n", name);
228 d->outputs.clks[output_index] = clock;
244 struct clk *clock; local
251 clock = clk_register_divider(d->dev, child_name, parent_name, 0,
254 if (IS_ERR(clock)) {
273 struct clk *clock; local
302 struct clk *clock; local
331 struct clk *clock; local
487 struct clk *clock; local
583 struct clk *clock; local
804 struct clk *clock; local
[all...]
/linux-master/drivers/gpu/drm/radeon/
H A Ddce6_afmt.h48 struct radeon_crtc *crtc, unsigned int clock);
50 struct radeon_crtc *crtc, unsigned int clock);
/linux-master/arch/x86/um/vdso/
H A Dum_vdso.c16 int __vdso_clock_gettime(clockid_t clock, struct __kernel_old_timespec *ts) argument
22 : "0" (__NR_clock_gettime), "D" (clock), "S" (ts)
/linux-master/arch/arm64/boot/dts/sprd/
H A Dsharkl64.dtsi61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <26000000>;
/linux-master/arch/sh/kernel/cpu/
H A Dclock.c3 * arch/sh/kernel/cpu/clock.c - SuperH clock framework
7 * This clock framework is derived from the OMAP version by:
12 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
17 #include <asm/clock.h>
27 pr_err("%s: CPU clock registration failed.\n", __func__);
35 pr_err("%s: machvec clock initialization failed.\n",
/linux-master/include/dt-bindings/clock/
H A Dr8a7791-cpg-mssr.h9 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a7793-cpg-mssr.h9 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a7792-cpg-mssr.h9 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a7743-cpg-mssr.h8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a7745-cpg-mssr.h8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a77470-cpg-mssr.h8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a7744-cpg-mssr.h8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a77970-cpg-mssr.h9 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a7794-cpg-mssr.h9 #include <dt-bindings/clock/renesas-cpg-mssr.h>
/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dr8a7743-cpg-mssr.h8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a7745-cpg-mssr.h8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a7744-cpg-mssr.h8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a7791-cpg-mssr.h9 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a77470-cpg-mssr.h8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a77970-cpg-mssr.h9 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a7793-cpg-mssr.h9 #include <dt-bindings/clock/renesas-cpg-mssr.h>
H A Dr8a7794-cpg-mssr.h9 #include <dt-bindings/clock/renesas-cpg-mssr.h>

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