Searched refs:set (Results 101 - 125 of 2137) sorted by last modified time
1234567891011>>
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | uvd_v6_0.c | 132 * uvd_v6_0_ring_set_wptr - set write pointer 146 * uvd_v6_0_enc_ring_set_wptr - set enc write pointer 846 /* set the write pointer delay */ 849 /* set the wb address */ 1656 .set = uvd_v6_0_set_interrupt_state,
|
H A D | uvd_v5_0.c | 78 * uvd_v5_0_ring_set_wptr - set write pointer 431 /* set the write pointer delay */ 434 /* set the wb address */ 912 .set = uvd_v5_0_set_interrupt_state,
|
H A D | uvd_v4_2.c | 80 * uvd_v4_2_ring_set_wptr - set write pointer 293 /* set uvd busy */ 392 /* set the ring address */ 804 .set = uvd_v4_2_set_interrupt_state,
|
H A D | uvd_v3_1.c | 66 * uvd_v3_1_ring_set_wptr - set write pointer 330 /* set uvd busy */ 429 /* set the ring address */ 523 .set = uvd_v3_1_set_interrupt_state,
|
H A D | si_dma.c | 749 .set = si_dma_set_trap_irq_state,
|
H A D | sdma_v6_0.c | 463 /* set the wb address whether it's enabled or not */ 478 /* before programing wptr to a less value, need set minor_ptr_update first */ 507 /* set minor_ptr_update to 0 after wptr programed */ 746 /* set RB registers */ 1255 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1555 .set = sdma_v6_0_set_trap_irq_state,
|
H A D | sdma_v5_2.c | 522 /* set the wb address whether it's enabled or not */ 535 /* before programing wptr to a less value, need set minor_ptr_update first */ 563 /* set minor_ptr_update to 0 after wptr programed */ 569 /* set utc l1 enable flag always to 1 */ 727 /* set RB registers */ 1233 DRM_INFO("use_doorbell being set to: [%s]\n", 1732 .set = sdma_v5_2_set_trap_irq_state,
|
H A D | sdma_v5_0.c | 715 /* set the wb address whether it's enabled or not */ 730 /* before programing wptr to a less value, need set minor_ptr_update first */ 761 /* set minor_ptr_update to 0 after wptr programed */ 765 /* set utc l1 enable flag always to 1 */ 892 /* set RB registers */ 1364 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1786 .set = sdma_v5_0_set_trap_irq_state,
|
H A D | sdma_v4_4_2.c | 635 /* set the wb address whether it's enabled or not */ 649 /* before programing wptr to a less value, need set minor_ptr_update first */ 671 /* set minor_ptr_update to 0 after wptr programed */ 729 /* set the wb address whether it's enabled or not */ 743 /* before programing wptr to a less value, need set minor_ptr_update first */ 760 /* set minor_ptr_update to 0 after wptr programed */ 899 /* set utc l1 enable flag always to 1 */ 1338 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1894 .set = sdma_v4_4_2_set_trap_irq_state, 1903 .set [all...] |
H A D | sdma_v4_0.c | 1060 /* set the wb address whether it's enabled or not */ 1074 /* before programing wptr to a less value, need set minor_ptr_update first */ 1090 /* set minor_ptr_update to 0 after wptr programed */ 1145 /* set the wb address whether it's enabled or not */ 1159 /* before programing wptr to a less value, need set minor_ptr_update first */ 1176 /* set minor_ptr_update to 0 after wptr programed */ 1366 /* set utc l1 enable flag always to 1 */ 1804 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 2393 .set = sdma_v4_0_set_trap_irq_state, 2402 .set [all...] |
H A D | sdma_v3_0.c | 681 /* set the wb address whether it's enabled or not */ 1599 .set = sdma_v3_0_set_trap_irq_state,
|
H A D | sdma_v2_4.c | 440 /* set the wb address whether it's enabled or not */ 1159 .set = sdma_v2_4_set_trap_irq_state,
|
H A D | mxgpu_nv.c | 48 * RCV_MSG_VALID filed of BIF_BX_PF_MAILBOX_CONTROL must already be set to 1 53 * RCV_MSG_VALID is set by host. 197 /* assume V1 in case host doesn't set version number */ 382 .set = xgpu_nv_set_mailbox_ack_irq, 387 .set = xgpu_nv_set_mailbox_rcv_irq,
|
H A D | mxgpu_ai.c | 49 * RCV_MSG_VALID filed of BIF_BX_PF0_MAILBOX_CONTROL must already be set to 1 54 * RCV_MSG_VALID is set by host. 188 /* version set to 0 since dummy */ 346 .set = xgpu_ai_set_mailbox_ack_irq, 351 .set = xgpu_ai_set_mailbox_rcv_irq,
|
H A D | jpeg_v5_0_0.c | 41 * jpeg_v5_0_0_early_init - set function pointers 395 * jpeg_v5_0_0_dec_ring_set_wptr - set write pointer 556 .set = jpeg_v5_0_0_set_interrupt_state,
|
H A D | jpeg_v4_0_3.c | 59 * jpeg_v4_0_3_early_init - set function pointers 626 * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer 1107 .set = jpeg_v4_0_3_set_interrupt_state,
|
H A D | jpeg_v4_0.c | 49 * jpeg_v4_0_early_init - set function pointers 497 /* 4, set resp to zero */ 596 * jpeg_v4_0_dec_ring_set_wptr - set write pointer 766 .set = jpeg_v4_0_set_ras_interrupt_state,
|
H A D | jpeg_v2_5.c | 51 * jpeg_v2_5_early_init - set function pointers 435 * jpeg_v2_5_dec_ring_set_wptr - set write pointer 736 .set = jpeg_v2_5_set_interrupt_state, 741 .set = jpeg_v2_6_set_ras_interrupt_state,
|
H A D | jpeg_v3_0.c | 43 * jpeg_v3_0_early_init - set function pointers 439 * jpeg_v3_0_dec_ring_set_wptr - set write pointer 600 .set = jpeg_v3_0_set_interrupt_state,
|
H A D | jpeg_v2_0.c | 41 * jpeg_v2_0_early_init - set function pointers 418 * jpeg_v2_0_dec_ring_set_wptr - set write pointer 802 .set = jpeg_v2_0_set_interrupt_state,
|
H A D | gmc_v9_0.c | 736 .set = gmc_v9_0_vm_fault_interrupt_state, 742 .set = gmc_v9_0_ecc_interrupt_state, 862 /* This path is needed before KIQ/MES/GFXOFF are set up */ 1716 /* set the gart size */ 1995 * only way to set the correct vram_width
|
H A D | gmc_v8_0.c | 308 /* reset the engine and set to writable */ 578 /* set the gart size */ 748 * gmc_v8_0_set_prt() - set PRT VM fault 858 /* XXX: set to enable PTE/PDE in system memory */ 894 /* set vm size, must be a multiple of 4 */ 1111 * Currently set to 4GB ((1 << 20) 4k pages). 1736 .set = gmc_v8_0_vm_fault_interrupt_state,
|
H A D | gmc_v7_0.c | 199 /* reset the engine and set to writable */ 388 /* set the gart size */ 534 * gmc_v7_0_set_prt - set PRT VM fault 664 /* set vm size, must be a multiple of 4 */ 999 * Currently set to 4GB ((1 << 20) 4k pages). 1373 .set = gmc_v7_0_vm_fault_interrupt_state,
|
H A D | gmc_v6_0.c | 172 /* reset the engine and set to writable */ 324 /* set the gart size */ 408 * gmc_v8_0_set_prt() - set PRT VM fault 519 /* set vm size, must be a multiple of 4 */ 1132 .set = gmc_v6_0_vm_fault_interrupt_state,
|
H A D | gfx_v9_4_3.c | 891 /* set up the compute queues - allocate horizontally across pipes */ 1566 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1599 /* set the pointer to the MQD */ 1603 /* set MQD vmid to 0 */ 1608 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1613 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1628 /* set the wb address whether it's enabled or not */ 1643 /* set the vmid for the queue */ 1650 /* set MIN_IB_AVAIL_SIZE */ 1655 /* set stati [all...] |
Completed in 277 milliseconds
1234567891011>>