| /u-boot/drivers/reset/ |
| H A D | reset-uclass.c | 13 #include <reset.h>
14 #include <reset-uclass.h>
86 ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
99 ret = ofnode_parse_phandle_with_args(node, "resets", "#reset-cells", 0,
113 count = ofnode_count_phandle_with_args(node, "resets", "#reset-cells",
157 index = dev_read_stringlist_search(dev, "reset-names", name);
245 /* check if reset has been previously requested */
366 UCLASS_DRIVER(reset) = { variable
368 .name = "reset",
|
| H A D | reset-npcm.c | 7 #include <reset-uclass.h>
59 /* Use id field as register offset and data field as reset bit positiion */
124 { .compatible = "nuvoton,npcm845-reset" },
125 { .compatible = "nuvoton,npcm750-reset" },
|
| H A D | reset-socfpga.c | 22 #include <reset-uclass.h>
36 * For compatibility with Kernels that don't support peripheral reset, this
37 * driver can keep the old behaviour of not asserting peripheral reset before
41 * For that, the reset driver checks the environment variable
43 * reset again once taken out of reset and all peripherals in 'permodrst' are
44 * taken out of reset before booting into the OS.
46 * Linux kernels without proper peripheral reset support for all drivers used.
146 .name = "socfpga-reset",
|
| H A D | reset-ti-sci.c | 3 * Texas Instruments System Control Interface (TI SCI) reset driver
8 * Loosely based on Linux kernel reset-ti-sci.c...
16 #include <reset-uclass.h>
22 * struct ti_sci_reset_data - reset controller information structure
57 * On TI SCI-based devices, the reset provider id field is used as a
58 * device ID, and the data field is used as the associated reset mask.
67 * ti_sci_reset_set() - program a device's reset
68 * @rst: Handle to a single reset signal
72 * reset using the TI SCI protocol. The device's reset i
[all...] |
| /u-boot/arch/sh/include/asm/ |
| H A D | cpu_sh7757.h | 70 unsigned short reset; member in struct:usb0_phy_regs
|
| H A D | cpu_sh7752.h | 79 unsigned short reset; member in struct:usb0_phy_regs
|
| H A D | cpu_sh7753.h | 79 unsigned short reset; member in struct:usb0_phy_regs
|
| /u-boot/arch/arm/mach-socfpga/include/mach/ |
| H A D | reset_manager_arria10.h | 9 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
30 * SocFPGA Arria10 reset IDs, bank mapping is as follows:
|
| /u-boot/arch/mips/mach-octeon/include/mach/ |
| H A D | cvmx-fpa1.h | 92 * CN68XXP1 should not reset the FPA (doing so may break
116 status.s.reset = 1;
|
| H A D | cvmx-lbk-defs.h | 147 u64 reset : 1; member in struct:cvmx_lbk_sft_rst::cvmx_lbk_sft_rst_s
|
| /u-boot/lib/efi_selftest/ |
| H A D | efi_selftest_textinputex.c | 129 ret = con_in_ex->reset(con_in_ex, true);
|
| /u-boot/arch/arm/include/asm/arch-imx8ulp/ |
| H A D | pcc.h | 204 int pcc_reset_peripheral(int pcc_controller, int pcc_clk_slot, bool reset);
|
| /u-boot/drivers/watchdog/ |
| H A D | max6370_wdt.c | 103 .reset = max6370_wdt_reset,
|
| H A D | arm_smc_wdt.c | 108 .reset = smcwd_reset,
|
| H A D | bcm2835_wdt.c | 98 .reset = bcm2835_wdt_reset,
|
| H A D | npcm_wdt.c | 103 .reset = npcm_wdt_reset,
|
| /u-boot/include/ |
| H A D | generic-phy.h | 58 * @reset: reset the phy (optional).
85 * PLL, taking a controller out of reset, routing, etc. This function
110 * reset - resets a PHY device without shutting down
112 * @phy: PHY port to be reset
114 * During runtime, the PHY may need to be reset in order to
119 int (*reset)(struct phy *phy); member in struct:phy_ops
228 * @phy: PHY port to be reset
|
| H A D | rtc.h | 49 * reset() - reset the RTC to a known-good state
58 int (*reset)(struct udevice *dev); member in struct:rtc_ops
126 * dm_rtc_reset() - reset the RTC to a known-good state
129 * it may need to be reset to a known good state. This function achieves this.
|
| /u-boot/drivers/ |
| H A D | Makefile | 61 obj-$(CONFIG_SPL_DM_RESET) += reset/
113 obj-y += reset/
|
| /u-boot/drivers/ddr/altera/ |
| H A D | sdram_agilex.c | 15 #include <reset.h>
65 * bit[9] = 1 if warm reset compiled into EMIF Cal Code
66 * bit[10] = 1 if warm reset is on during generation in EMIF Cal
|
| /u-boot/drivers/pci/ |
| H A D | pcie_dw_sifive.c | 27 #include <reset.h>
39 /* reset, power, clock resources */
44 struct reset_ctl reset; member in struct:pcie_sifive
82 /* pcie reset */
89 /* phy reset */
348 /* Power on reset */
359 * assert hold_phy_rst (hold the controller LTSSM in reset
365 ret = reset_deassert(&sv->reset);
367 dev_err(dev, "failed to deassert reset");
466 gpio_request_by_name(dev, "reset
[all...] |
| /u-boot/drivers/phy/ |
| H A D | bcm6318-usbh-phy.c | 17 #include <reset.h>
114 /* perform reset */
|
| H A D | phy-rcar-gen3.c | 15 #include <reset.h>
|
| /u-boot/drivers/rtc/ |
| H A D | pl031.c | 117 .reset = pl031_reset,
|
| /u-boot/arch/arm/mach-mvebu/ |
| H A D | system-controller.c | 11 #include <reset-uclass.h>
101 .name = "mvebu-reset",
123 /* Loop while waiting for the reset */
146 /* bind also mvebu-reset, with the same ofnode */
148 ret = device_bind_driver_to_node(dev, "mvebu-reset",
149 "mvebu-reset", dev_ofnode(dev),
|