/u-boot/arch/arm/mach-tegra/ |
H A D | fuse.c | 45 u32 reg; local 52 reg = readl_relaxed(NV_PA_CLK_RST_BASE + 0x48); 53 reg |= BIT(28); 54 writel(reg, NV_PA_CLK_RST_BASE + 0x48); 64 u32 reg; local 129 reg = tegra_fuse_readl(FUSE_LOT_CODE_0) << 2; 132 u32 digit = (reg & 0xFC000000) >> 26; 135 reg <<= 6;
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/u-boot/drivers/video/exynos/ |
H A D | exynos_fb.c | 100 struct exynos_fb *reg; member in struct:exynos_fb_priv 106 struct exynos_fb *reg = priv->reg; local 118 writel(cfg, ®->dualrgb); 124 struct exynos_fb *reg = priv->reg; local 130 writel(cfg, ®->dp_mie_clkcon); 136 struct exynos_fb *reg = priv->reg; local 140 cfg = readl((unsigned int)® 191 struct exynos_fb *reg = priv->reg; local 206 struct exynos_fb *reg = priv->reg; local 260 struct exynos_fb *reg = priv->reg; local 272 struct exynos_fb *reg = priv->reg; local 287 struct exynos_fb *reg = priv->reg; local 299 struct exynos_fb *reg = priv->reg; local 316 struct exynos_fb *reg = priv->reg; local 326 struct exynos_fb *reg = priv->reg; local 382 struct exynos_fb *reg = priv->reg; local [all...] |
/u-boot/board/freescale/common/ |
H A D | ngpixis.h | 56 u8 pixis_read(unsigned int reg); 57 void pixis_write(unsigned int reg, u8 value); 59 #define PIXIS_READ(reg) pixis_read(offsetof(ngpixis_t, reg)) 60 #define PIXIS_WRITE(reg, value) pixis_write(offsetof(ngpixis_t, reg), value)
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/u-boot/board/freescale/p2041rdb/ |
H A D | cpld.h | 50 u8 cpld_read(unsigned int reg); 51 void cpld_write(unsigned int reg, u8 value); 53 #define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg)) 54 #define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value)
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/u-boot/arch/arm/mach-uniphier/debug-uart/ |
H A D | debug-uart.c | 34 void __iomem *reg = sg_base + SG_PINCTRL_BASE + local 39 tmp = readl(reg); 42 writel(tmp, reg); 48 void __iomem *reg = sg_base + SG_IECTRL + pin / 32 * 4; local 51 tmp = readl(reg); 53 writel(tmp, reg);
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/u-boot/arch/mips/mach-mscc/ |
H A D | reset.c | 14 register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL); local 16 reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M; 17 reg |= ICPU_GENERAL_CTRL_IF_SI_OWNER(1); 19 reg |= ICPU_GENERAL_CTRL_BOOT_MODE_ENA; 20 writel(reg, BASE_CFG + ICPU_GENERAL_CTRL); 22 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
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/u-boot/drivers/power/pmic/ |
H A D | tps80031.c | 17 static int tps80031_write(struct udevice *dev, uint reg, const uint8_t *buff, argument 22 ret = dm_i2c_write(dev, reg, buff, len); 24 log_debug("write error to device: %p register: %#x!\n", dev, reg); 31 static int tps80031_read(struct udevice *dev, uint reg, uint8_t *buff, int len) argument 35 ret = dm_i2c_read(dev, reg, buff, len); 37 log_debug("read error from device: %p register: %#x!\n", dev, reg);
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H A D | max77686.c | 29 static int max77686_write(struct udevice *dev, uint reg, const uint8_t *buff, argument 32 if (dm_i2c_write(dev, reg, buff, len)) { 33 pr_err("write error to device: %p register: %#x!\n", dev, reg); 40 static int max77686_read(struct udevice *dev, uint reg, uint8_t *buff, int len) argument 42 if (dm_i2c_read(dev, reg, buff, len)) { 43 pr_err("read error from device: %p register: %#x!\n", dev, reg);
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H A D | lp873x.c | 25 static int lp873x_write(struct udevice *dev, uint reg, const uint8_t *buff, argument 28 if (dm_i2c_write(dev, reg, buff, len)) { 29 pr_err("write error to device: %p register: %#x!\n", dev, reg); 36 static int lp873x_read(struct udevice *dev, uint reg, uint8_t *buff, int len) argument 38 if (dm_i2c_read(dev, reg, buff, len)) { 39 pr_err("read error from device: %p register: %#x!\n", dev, reg);
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H A D | act8846.c | 26 static int act8846_write(struct udevice *dev, uint reg, const uint8_t *buff, argument 29 if (dm_i2c_write(dev, reg, buff, len)) { 30 debug("write error to device: %p register: %#x!\n", dev, reg); 37 static int act8846_read(struct udevice *dev, uint reg, uint8_t *buff, int len) argument 39 if (dm_i2c_read(dev, reg, buff, len)) { 40 debug("read error from device: %p register: %#x!\n", dev, reg);
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H A D | lp87565.c | 24 static int lp87565_write(struct udevice *dev, uint reg, const uint8_t *buff, argument 29 ret = dm_i2c_write(dev, reg, buff, len); 31 pr_err("write error to device: %p register: %#x!\n", dev, reg); 36 static int lp87565_read(struct udevice *dev, uint reg, uint8_t *buff, int len) argument 40 ret = dm_i2c_read(dev, reg, buff, len); 42 pr_err("read error from device: %p register: %#x!\n", dev, reg);
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H A D | fan53555.c | 23 static int pmic_fan53555_read(struct udevice *dev, uint reg, argument 26 if (dm_i2c_read(dev, reg, buff, len)) { 27 pr_err("%s: read error for register: %#x!\n", dev->name, reg); 34 static int pmic_fan53555_write(struct udevice *dev, uint reg, argument 37 if (dm_i2c_write(dev, reg, buff, len)) { 38 pr_err("%s: write error for register: %#x!", dev->name, reg);
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H A D | pmic_qcom.c | 25 static int pmic_qcom_write(struct udevice *dev, uint reg, const uint8_t *buff, argument 34 (reg & PID_MASK) >> PID_SHIFT, reg & REG_MASK, 38 static int pmic_qcom_read(struct udevice *dev, uint reg, uint8_t *buff, int len) argument 47 (reg & PID_MASK) >> PID_SHIFT, reg & REG_MASK); 72 * dev_read_addr() can't be used here because the reg property actually 76 ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, &priv->usid);
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H A D | rn5t567.c | 21 static int rn5t567_write(struct udevice *dev, uint reg, const uint8_t *buff, argument 26 ret = dm_i2c_write(dev, reg, buff, len); 28 debug("write error to device: %p register: %#x!\n", dev, reg); 35 static int rn5t567_read(struct udevice *dev, uint reg, uint8_t *buff, int len) argument 39 ret = dm_i2c_read(dev, reg, buff, len); 41 debug("read error from device: %p register: %#x!\n", dev, reg);
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H A D | s2mps11.c | 28 static int s2mps11_write(struct udevice *dev, uint reg, const uint8_t *buff, argument 33 ret = dm_i2c_write(dev, reg, buff, len); 35 pr_err("write error to device: %p register: %#x!\n", dev, reg); 40 static int s2mps11_read(struct udevice *dev, uint reg, uint8_t *buff, int len) argument 44 ret = dm_i2c_read(dev, reg, buff, len); 46 pr_err("read error from device: %p register: %#x!\n", dev, reg);
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H A D | sandbox.c | 31 static int sandbox_pmic_write(struct udevice *dev, uint reg, argument 34 if (dm_i2c_write(dev, reg, buff, len)) { 35 log_err("write error to device: %p register: %#x!\n", dev, reg); 42 static int sandbox_pmic_read(struct udevice *dev, uint reg, argument 45 if (dm_i2c_read(dev, reg, buff, len)) { 46 log_err("read error from device: %p register: %#x!\n", dev, reg);
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H A D | s5m8767.c | 28 static int s5m8767_write(struct udevice *dev, uint reg, const uint8_t *buff, argument 31 if (dm_i2c_write(dev, reg, buff, len)) { 32 pr_err("write error to device: %p register: %#x!\n", dev, reg); 39 static int s5m8767_read(struct udevice *dev, uint reg, uint8_t *buff, int len) argument 41 if (dm_i2c_read(dev, reg, buff, len)) { 42 pr_err("read error from device: %p register: %#x!\n", dev, reg);
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H A D | tps65090.c | 27 static int tps65090_write(struct udevice *dev, uint reg, const uint8_t *buff, argument 30 if (dm_i2c_write(dev, reg, buff, len)) { 31 pr_err("write error to device: %p register: %#x!\n", dev, reg); 38 static int tps65090_read(struct udevice *dev, uint reg, uint8_t *buff, int len) argument 42 ret = dm_i2c_read(dev, reg, buff, len); 45 dev, reg);
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H A D | tps65219.c | 29 static int tps65219_write(struct udevice *dev, uint reg, const uint8_t *buff, argument 32 if (dm_i2c_write(dev, reg, buff, len)) { 33 pr_err("write error to device: %p register: %#x!\n", dev, reg); 40 static int tps65219_read(struct udevice *dev, uint reg, uint8_t *buff, int len) argument 42 if (dm_i2c_read(dev, reg, buff, len)) { 43 pr_err("read error from device: %p register: %#x!\n", dev, reg);
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/u-boot/drivers/axi/ |
H A D | axi-emul-uclass.c | 20 u32 reg[2]; local 47 ret = dev_read_u32_array(dev, "reg", reg, ARRAY_SIZE(reg)); 49 debug("%s: Could not read 'reg' property of %s\n", 58 if (address >= reg[0] && address <= reg[0] + reg[1] - offset) {
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/u-boot/drivers/spi/ |
H A D | kirkwood_spi.c | 35 static void _spi_cs_activate(struct kwspi_registers *reg) argument 37 setbits_le32(®->ctrl, KWSPI_CSN_ACT); 40 static void _spi_cs_deactivate(struct kwspi_registers *reg) argument 42 clrbits_le32(®->ctrl, KWSPI_CSN_ACT); 45 static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, argument 54 _spi_cs_activate(reg); 60 clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE); 70 clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ); 71 writel(tmpdout, ®->dout); /* Write the data out */ 81 if (readl(® 114 struct kwspi_registers *reg = plat->spireg; local 188 struct kwspi_registers *reg = plat->spireg; local 221 struct kwspi_registers *reg = plat->spireg; local 281 struct kwspi_registers *reg = plat->spireg; local [all...] |
/u-boot/arch/arm/mach-imx/mx7ulp/ |
H A D | pcc.c | 84 u32 reg, val; local 89 reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; 91 val = readl(reg); 93 clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n", 94 clk, reg, val, enable); 104 writel(val, reg); 114 u32 reg, val, i, clksrc_type; local 138 reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; 140 val = readl(reg); 142 clk_debug("pcc_clock_sel: clk %d, reg 163 u32 reg, val; local 199 u32 reg, val; local 215 u32 reg, val, clksrc_type; local 256 u32 reg, val, rate, frac, div; local [all...] |
/u-boot/drivers/video/ |
H A D | atmel_lcdfb.c | 49 #define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg)) 50 #define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg)) 56 void *reg = (void *)addr; local 59 lcdc_writel(reg, ATMEL_LCDC_PWRCON, 63 while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY) 66 lcdc_writel(reg, ATMEL_LCDC_DMACON, 0); 69 lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST); 75 lcdc_writel(reg, ATMEL_LCDC_DMAFRMCF [all...] |
/u-boot/arch/arm/mach-stm32mp/ |
H A D | dram_init.c | 49 phys_addr_t reg; local 67 reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE); 69 if (!reg) 70 reg = gd->ram_top - size; 74 mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION); 76 return reg + size;
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/u-boot/arch/arm/cpu/armv7/ |
H A D | virt-v7.c | 21 unsigned int reg; local 23 asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg)); 24 return reg; 92 unsigned int reg; local 97 reg = read_id_pfr1(); 98 if ((reg & 0xF0) == 0) {
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