Searched refs:enable (Results 101 - 125 of 551) sorted by relevance

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/u-boot/arch/sandbox/include/asm/
H A Dtest.h138 * @enable: true if the PWM is enabled
277 * to work as for other architectures, so this function can be used to enable
280 * @enable: true to enable, false to disable
282 void sandbox_set_enable_memio(bool enable);
335 * @enable: true to enable Ethernet, false to disable
337 void sandbox_set_eth_enable(bool enable);
356 * @enable: true to bind the SPI flash bootdevs, false to skip
358 void sandbox_sf_set_enable_bootdevs(bool enable);
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/u-boot/drivers/clk/renesas/
H A Drenesas-cpg-mssr.c94 struct cpg_mssr_info *info, bool enable)
105 clkid, reg, bit, enable ? "ON" : "OFF");
107 if (enable) {
93 renesas_clk_endisable(struct clk *clk, void __iomem *base, struct cpg_mssr_info *info, bool enable) argument
/u-boot/drivers/clk/imx/
H A Dclk-composite-93.c51 static void imx93_clk_composite_gate_endisable(struct clk *clk, int enable) argument
58 if (enable)
83 .enable = imx93_clk_composite_gate_enable,
H A Dclk-gate-93.c51 static void imx93_clk_gate_do_hardware(struct clk *clk, bool enable) argument
58 val = enable ? LPM_SETTING_ON : LPM_SETTING_OFF;
63 if (enable)
108 .enable = imx93_clk_gate_enable,
H A Dclk-imx8.c30 __weak int __imx8_clk_enable(struct clk *clk, bool enable) argument
85 .enable = imx8_clk_enable,
/u-boot/arch/arm/mach-socfpga/
H A Dreset_manager_s10.c60 void socfpga_bridges_reset(int enable) argument
63 u64 arg = enable;
73 if (enable) {
/u-boot/drivers/power/regulator/
H A Dtps65090_regulator.c87 static int tps65090_fet_set_enable(struct udevice *dev, bool enable) argument
95 debug("%s: fet_id=%d, enable=%d\n", __func__, fet_id, enable);
99 ret = tps65090_fet_set(pmic, fet_id, enable);
H A Dstm32-vrefbuf.c42 static int stm32_vrefbuf_set_enable(struct udevice *dev, bool enable) argument
48 if (enable && !(readl(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR)) {
61 enable ? STM32_ENVR : 0);
62 if (!enable)
139 dev_err(dev, "Can't enable clock: %d\n", ret);
152 dev_err(dev, "Can't enable vdda-supply: %d\n", ret);
/u-boot/drivers/clk/
H A Dclk.c117 static int ccf_clk_endisable(struct clk *clk, bool enable) argument
124 return enable ? clk_enable(c) : clk_disable(c);
141 .enable = ccf_clk_enable,
H A Dclk-gate.c35 * enable - clk_enable and clk_disable are functional & control gating
43 * For enabling clock, enable = 1
47 * For disabling clock, enable = 0
51 * So, result is always: enable xor set2dis.
53 static void clk_gate_endisable(struct clk *clk, int enable) argument
59 set ^= enable;
116 .enable = clk_gate_enable,
H A Dclk_octeon.c43 .enable = octeon_clk_enable,
/u-boot/board/compulab/imx8mm-cl-iot-gate/
H A Deeprom_spl.c23 static void cl_eeprom_we(int enable) argument
28 gpio_direction_output(EEPROM_WP_GPIO, enable);
34 gpio_direction_output(EEPROM_WP_GPIO, enable);
/u-boot/include/
H A Ddma-uclass.h70 * enable() - Enable a DMA Channel.
75 int (*enable)(struct dma *dma); member in struct:dma_ops
/u-boot/drivers/video/
H A Dbacklight_gpio.c56 .enable = gpio_backlight_enable,
H A Dsimple_panel.c23 struct gpio_desc enable; member in struct:simple_panel_priv
32 dm_gpio_set_value(&priv->enable, 1);
47 dm_gpio_set_value(&priv->enable, 1);
147 ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable,
150 debug("%s: Warning: cannot get enable GPIO: ret=%d\n",
169 debug("%s: failed to enable regulator '%s' %d\n",
H A Ddisplay-uclass.c30 if (!ops || !ops->enable)
32 ret = ops->enable(dev, panel_bpp, timing);
/u-boot/drivers/mmc/
H A Dmmc-pwrseq.c21 static int mmc_pwrseq_set_power(struct udevice *dev, bool enable) argument
H A Dmmc_boot.c120 * for enable. Note that this is a write-once field for non-zero values.
124 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) argument
127 enable);
/u-boot/arch/x86/include/asm/
H A Dpnp_def.h57 static inline void pnp_set_enable(uint16_t dev, int enable) argument
59 pnp_write_config(dev, PNP_IDX_EN, enable ? 1 : 0);
/u-boot/drivers/net/octeontx/
H A Dnicvf_queues.h87 /* Queue enable/disable */
235 bool enable; member in struct:rbdr
247 bool enable; member in struct:rcv_queue
262 bool enable; member in struct:cmp_queue
271 bool enable; member in struct:snd_queue
285 bool enable; member in struct:queue_set
317 int nicvf_config_data_transfer(struct nicvf *nic, bool enable);
318 void nicvf_qset_config(struct nicvf *nic, bool enable);
320 int qidx, bool enable);
/u-boot/arch/mips/mach-octeon/include/mach/
H A Dcvmx-helper-bgx.h38 * Bringup and enable a SGMII interface. After this call packet
99 * Bringup and enable a XAUI interface. After this call packet
295 * @param enable true to enable autonegotiation, false to disable it
299 int cvmx_helper_set_autonegotiation(int xiface, int index, bool enable);
306 * @param enable set to true to enable FEC, false to disable
313 int cvmx_helper_set_fec(int xiface, int index, bool enable);
/u-boot/drivers/pwm/
H A Dtegra_pwm.c44 static int tegra_pwm_set_enable(struct udevice *dev, uint channel, bool enable) argument
53 enable ? PWM_ENABLE_MASK : 0);
/u-boot/drivers/usb/phy/
H A Drockchip_usb2_phy.c25 unsigned int enable; member in struct:usb2phy_reg
69 tmp = en ? reg->enable : reg->disable;
114 /* enable software control */
/u-boot/drivers/watchdog/
H A Dstarfive_wdt.c18 * [0]: reset enable;
19 * [1]: interrupt enable && watchdog enable
48 unsigned int control; /* Watchdog Control Resgister for reset enable */
51 unsigned int enable; /* Watchdog Enable Register */ member in struct:starfive_wdt_variant
80 .enable = STARFIVE_WDT_JH7110_CONTROL,
126 /* enable watchdog interrupt to reset/reboot */
167 /* enable watchdog */
172 val = readl(wdt->base + wdt->variant->enable);
174 writel(val, wdt->base + wdt->variant->enable);
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/u-boot/drivers/video/exynos/
H A Dexynos_dp_lowlevel.c22 unsigned int enable)
29 /* enable video input */
30 if (enable)
38 void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs, unsigned int enable) argument
40 /* enable video bist */
46 /* enable video bist */
47 if (enable)
55 void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs, unsigned int enable) argument
61 if (enable)
173 void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable) argument
21 exynos_dp_enable_video_input(struct exynos_dp *dp_regs, unsigned int enable) argument
188 exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs, unsigned int block, u32 enable) argument
254 exynos_dp_set_pll_power(struct exynos_dp *dp_regs, unsigned int enable) argument
966 exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs, unsigned char enable) argument
980 exynos_dp_enable_scrambling(struct exynos_dp *dp_regs, unsigned int enable) argument
1212 exynos_dp_enable_video_master(struct exynos_dp *dp_regs, unsigned int enable) argument
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