1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2016 Rockchip Electronics Co., Ltd
4 */
5
6#include <common.h>
7#include <hang.h>
8#include <log.h>
9#include <asm/global_data.h>
10#include <asm/io.h>
11#include <linux/bitops.h>
12#include <linux/delay.h>
13
14#include "../gadget/dwc2_udc_otg_priv.h"
15
16DECLARE_GLOBAL_DATA_PTR;
17
18#define BIT_WRITEABLE_SHIFT	16
19
20struct usb2phy_reg {
21	unsigned int offset;
22	unsigned int bitend;
23	unsigned int bitstart;
24	unsigned int disable;
25	unsigned int enable;
26};
27
28/**
29 * struct rockchip_usb2_phy_cfg: usb-phy port configuration
30 * @port_reset: usb otg per-port reset register
31 * @soft_con: software control usb otg register
32 * @suspend: phy suspend register
33 */
34struct rockchip_usb2_phy_cfg {
35	struct usb2phy_reg port_reset;
36	struct usb2phy_reg soft_con;
37	struct usb2phy_reg suspend;
38};
39
40struct rockchip_usb2_phy_dt_id {
41	char		compatible[128];
42	const void	*data;
43};
44
45static const struct rockchip_usb2_phy_cfg rk3066a_pdata = {
46	.port_reset	= {0x00, 12, 12, 0, 1},
47	.soft_con	= {0x08, 2, 2, 0, 1},
48	.suspend	= {0x08, 8, 3, (0x01 << 3), (0x2A << 3)},
49};
50
51static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
52	.port_reset     = {0x00, 12, 12, 0, 1},
53	.soft_con       = {0x08, 2, 2, 0, 1},
54	.suspend	= {0x0c, 5, 0, 0x01, 0x2A},
55};
56
57static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = {
58	{ .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
59	{ .compatible = "rockchip,rk3188-usb-phy", .data = &rk3288_pdata },
60	{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
61	{}
62};
63
64static void property_enable(struct dwc2_plat_otg_data *pdata,
65				  const struct usb2phy_reg *reg, bool en)
66{
67	unsigned int val, mask, tmp;
68
69	tmp = en ? reg->enable : reg->disable;
70	mask = GENMASK(reg->bitend, reg->bitstart);
71	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
72
73	writel(val, pdata->regs_phy + reg->offset);
74}
75
76
77void otg_phy_init(struct dwc2_udc *dev)
78{
79	struct dwc2_plat_otg_data *pdata = dev->pdata;
80	struct rockchip_usb2_phy_cfg *phy_cfg = NULL;
81	struct rockchip_usb2_phy_dt_id *of_id;
82	int i;
83
84	for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) {
85		of_id = &rockchip_usb2_phy_dt_ids[i];
86		if (ofnode_device_is_compatible(pdata->phy_of_node,
87						of_id->compatible)){
88			phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data;
89			break;
90		}
91	}
92	if (!phy_cfg) {
93		debug("Can't find device platform data\n");
94
95		hang();
96		return;
97	}
98	pdata->priv = phy_cfg;
99	/* disable software control */
100	property_enable(pdata, &phy_cfg->soft_con, false);
101
102	/* reset otg port */
103	property_enable(pdata, &phy_cfg->port_reset, true);
104	mdelay(1);
105	property_enable(pdata, &phy_cfg->port_reset, false);
106	udelay(1);
107}
108
109void otg_phy_off(struct dwc2_udc *dev)
110{
111	struct dwc2_plat_otg_data *pdata = dev->pdata;
112	struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv;
113
114	/* enable software control */
115	property_enable(pdata, &phy_cfg->soft_con, true);
116	/* enter suspend */
117	property_enable(pdata, &phy_cfg->suspend, true);
118}
119