/u-boot/arch/arm/mach-uniphier/clk/ |
H A D | dpll-sld8.c | 7 #include <linux/delay.h>
|
H A D | clk-ld11.c | 8 #include <linux/delay.h>
|
H A D | dpll-pro4.c | 7 #include <linux/delay.h>
|
H A D | dpll-ld4.c | 7 #include <linux/delay.h>
|
/u-boot/include/ |
H A D | xyzModem.h | 28 #include <linux/delay.h>
|
/u-boot/board/asus/grouper/ |
H A D | grouper-spl-ti.c | 14 #include <linux/delay.h>
|
H A D | grouper-spl-max.c | 14 #include <linux/delay.h>
|
/u-boot/board/asus/transformer-t30/ |
H A D | transformer-t30-spl.c | 14 #include <linux/delay.h>
|
/u-boot/board/lg/x3-t30/ |
H A D | x3-t30-spl.c | 14 #include <linux/delay.h>
|
/u-boot/lib/ |
H A D | panic.c | 16 #include <linux/delay.h>
|
/u-boot/drivers/power/ |
H A D | mt6323.c | 9 #include <linux/delay.h>
|
/u-boot/drivers/usb/gadget/ |
H A D | bcm_udc_otg_phy.c | 11 #include <linux/delay.h>
|
/u-boot/board/msc/sm2s_imx8mp/ |
H A D | sm2s_imx8mp.c | 20 #include <linux/delay.h>
|
/u-boot/arch/powerpc/lib/ |
H A D | time.c | 11 #include <linux/delay.h> 36 * We implement the delay by converting the delay (the number of
|
/u-boot/board/dfi/dfi-bt700/ |
H A D | dfi-bt700.c | 13 #include <linux/delay.h>
|
/u-boot/arch/powerpc/cpu/mpc85xx/ |
H A D | spl_minimal.c | 11 #include <linux/delay.h>
|
/u-boot/arch/arm/mach-tegra/tegra20/ |
H A D | cpu.c | 10 #include <linux/delay.h> 23 * The TI PMU65861C needs a 3.75ms delay between enabling 24 * the power rail and enabling the CPU clock. This delay
|
/u-boot/arch/arm/mach-mvebu/serdes/a38x/ |
H A D | seq_exec.c | 11 #include <linux/delay.h> 24 /* Array for mapping the operation (write, poll or delay) functions */ 72 u32 delay; local 74 /* Getting delay op params from the input parameter */ 75 delay = params->wait_time; 77 printf("Delay: %d\n", delay); 79 mdelay(delay);
|
/u-boot/drivers/net/ |
H A D | eth-phy-uclass.c | 17 #include <linux/delay.h> 150 dev_read_u32_default(dev, "reset-delay-us", 0); 152 dev_read_u32_default(dev, "reset-post-delay-us", 0); 161 u32 delay; local 171 delay = value ? uc_priv->reset_assert_delay : uc_priv->reset_deassert_delay; 172 if (delay) 173 udelay(delay);
|
/u-boot/drivers/i2c/ |
H A D | nx_i2c.c | 11 #include <linux/delay.h> 31 #define SDADLY_CLKSTEP 5 /* SDA delay: Reg. val. is multiple of 5 clks */ 32 #define SDADLY_MAX 3 /* SDA delay: Max. reg. value is 3 */ 56 /* S5P6818: Offset 0x10 is Line Control Register (SDA-delay, Filter) */ 121 /* Set SDA line delay, not available at S5P4418 */ 127 uint delay = 0; local 135 /* delay = number of pclks required for sda_delay [ns] */ 136 delay = DIV_ROUND_UP(bus->sda_delay, t_pclk); 137 /* delay = register value (step of 5 clocks) */ 138 delay [all...] |
/u-boot/cmd/ |
H A D | bootmenu.c | 18 #include <linux/delay.h> 97 if (menu->delay >= 0) { 321 static struct bootmenu_data *bootmenu_create(int delay) argument 334 menu->delay = delay; 471 static enum bootmenu_ret bootmenu_show(int delay) argument 488 /* If delay is 0 do not create menu, just run first entry */ 489 if (delay == 0) { 504 bootmenu = bootmenu_create(delay); 508 menu = menu_create(NULL, bootmenu->delay, 624 int delay = 10; local [all...] |
/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 92 u32 delay, phase, pup, cs; local 111 delay = reg & PUP_DELAY_MASK; 117 dram_info->rl_val[cs][pup][D] = delay; 182 u32 reg, cs, ecc, pup_num, phase, delay, pup; local 227 /* Set current Ready delay */ 292 delay = dram_info->rl_val[cs][pup][D]; 294 delay); 338 int *counter_in_progress, int final_delay, u32 delay, 359 info->rl_val[cs][idx][DS] = delay; 404 u32 reg, delay, phas local 336 overrun(u32 cs, MV_DRAM_INFO *info, u32 pup, u32 locked_pups, u32 *locked_sum, u32 ecc, int *first_octet_locked, int *counter_in_progress, int final_delay, u32 delay, u32 phase) argument 756 u32 reg, delay, phase, sum, pup, rd_sample_delay, add, locked_pups, local [all...] |
H A D | ddr3_write_leveling.c | 13 #include <linux/delay.h> 68 u32 reg, phase, delay, cs, pup; local 122 delay = reg & PUP_DELAY_MASK; 124 dram_info->wl_val[cs][pup][D] = delay; 188 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; local 354 delay = 363 phase, delay); 370 delay = 377 && (delay <= 383 delay 476 u32 reg, phase, delay, cs, pup, pup_num; local 1129 u32 reg, pup_num, delay, phase, phaseMax, max_pup_num, pup, local [all...] |
/u-boot/arch/x86/cpu/intel_common/ |
H A D | mrc.c | 255 int ret, delay; local 261 delay = dev_read_u32_default(dev, "fspm,training-delay", 0); 263 if (delay) 264 printf("SDRAM training (%d seconds)...", delay); 268 if (delay) 269 printf("(%d seconds)...", delay); 273 if (delay)
|
/u-boot/common/ |
H A D | menu.c | 12 #include <linux/delay.h> 346 * timeout - A delay in seconds to wait for user input. If 0, timeout is 436 while (menu->delay > 0) { 439 printf("Hit any key to stop autoboot: %d ", menu->delay); 449 menu->delay = -1; 471 if (menu->delay < 0) 474 --menu->delay; 480 if (menu->delay == 0)
|