1309577Sglebius// SPDX-License-Identifier: GPL-2.0 2309577Sglebius/* 3309577Sglebius * Based on vendor support provided by AVNET Embedded 4309577Sglebius * 5309577Sglebius * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH 6309577Sglebius * Copyright 2021 General Electric Company 7309577Sglebius * Copyright 2021 Collabora Ltd. 8309577Sglebius */ 9309577Sglebius 10309577Sglebius#include <common.h> 11309577Sglebius#include <errno.h> 12309577Sglebius#include <miiphy.h> 13309577Sglebius#include <netdev.h> 14309577Sglebius#include <asm/arch/clock.h> 15309577Sglebius#include <asm/arch/imx8mp_pins.h> 16309577Sglebius#include <asm/arch/sys_proto.h> 17309577Sglebius#include <asm/mach-imx/gpio.h> 18309577Sglebius#include <asm/mach-imx/iomux-v3.h> 19309577Sglebius#include <asm-generic/gpio.h> 20309577Sglebius#include <linux/delay.h> 21309577Sglebius 22309577SglebiusDECLARE_GLOBAL_DATA_PTR; 23309577Sglebius 24309577Sglebiusstatic void setup_fec(void) 25309577Sglebius{ 26309577Sglebius struct iomuxc_gpr_base_regs *gpr = 27309577Sglebius (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 28309577Sglebius 29309577Sglebius /* Enable RGMII TX clk output */ 30309577Sglebius setbits_le32(&gpr->gpr[1], BIT(22)); 31309577Sglebius} 32309577Sglebius 33309577Sglebiusint board_phy_config(struct phy_device *phydev) 34309577Sglebius{ 35309577Sglebius if (phydev->drv->config) 36309577Sglebius phydev->drv->config(phydev); 37309577Sglebius return 0; 38309577Sglebius} 39309577Sglebius 40309577Sglebiusint board_init(void) 41309577Sglebius{ 42309577Sglebius setup_fec(); 43309577Sglebius 44309577Sglebius return 0; 45309577Sglebius} 46309577Sglebius