Searched refs:CLK_TOP_GCPU_SEL (Results 26 - 30 of 30) sorted by relevance
12
| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 110 #define CLK_TOP_GCPU_SEL 100 macro
|
| H A D | mt2712-clk.h | 197 #define CLK_TOP_GCPU_SEL 166 macro
|
| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 474 MUX_GATE(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0e0, 0, 3, 7),
|
| H A D | clk-mt8518.c | 1225 MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3),
1474 GATE_TOP5_I(CLK_TOP_GCPU, CLK_TOP_GCPU_SEL, 26),
|
| H A D | clk-mt8512.c | 550 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents,
|
Completed in 280 milliseconds
12