| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt8518-clk.h | 97 #define CLK_TOP_ETH_SEL 75 macro
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| H A D | mt7622-clk.h | 72 #define CLK_TOP_ETH_SEL 59 macro
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| H A D | mediatek,mt8365-clk.h | 109 #define CLK_TOP_ETH_SEL 99 macro
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| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt7622-clk.h | 72 #define CLK_TOP_ETH_SEL 59 macro
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| H A D | mediatek,mt8365-clk.h | 109 #define CLK_TOP_ETH_SEL 99 macro
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| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt7622-clk.h | 72 #define CLK_TOP_ETH_SEL 59 macro
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| H A D | mediatek,mt8365-clk.h | 109 #define CLK_TOP_ETH_SEL 99 macro
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| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt7622-clk.h | 72 #define CLK_TOP_ETH_SEL 59 macro
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| H A D | mediatek,mt8365-clk.h | 109 #define CLK_TOP_ETH_SEL 99 macro
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| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt7622-clk.h | 72 #define CLK_TOP_ETH_SEL 59 macro
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| H A D | mediatek,mt8365-clk.h | 109 #define CLK_TOP_ETH_SEL 99 macro
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| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt7622-clk.h | 72 #define CLK_TOP_ETH_SEL 59 macro
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| H A D | mediatek,mt8365-clk.h | 109 #define CLK_TOP_ETH_SEL 99 macro
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| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt7622-clk.h | 72 #define CLK_TOP_ETH_SEL 59 macro
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| H A D | mediatek,mt8365-clk.h | 109 #define CLK_TOP_ETH_SEL 99 macro
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| /u-boot/include/dt-bindings/clock/ |
| H A D | mt7622-clk.h | 72 #define CLK_TOP_ETH_SEL 59 macro
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| H A D | mediatek,mt8365-clk.h | 109 #define CLK_TOP_ETH_SEL 99 macro
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| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mt7622-clk.h | 71 #define CLK_TOP_ETH_SEL 59 macro
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| H A D | mediatek,mt8365-clk.h | 109 #define CLK_TOP_ETH_SEL 99 macro
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8516.c | 110 FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2),
514 MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
700 GATE_TOP3(CLK_TOP_RG_ETH, CLK_TOP_ETH_SEL, 2),
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| H A D | clk-mt7622.c | 315 MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
504 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5),
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| H A D | clk-mt8365.c | 472 MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x0d0, 24, 3, 31),
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| H A D | clk-mt7629.c | 368 MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
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| H A D | clk-mt8518.c | 1194 MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
1449 GATE_TOP4(CLK_TOP_ETH, CLK_TOP_ETH_SEL, 2),
|